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LTC2264CUJ-14#TRPBF

产品描述IC ADC 14BIT SER/PAR 40M 40-QFN
产品类别模拟混合信号IC    转换器   
文件大小1MB,共32页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
标准
下载文档 详细参数 全文预览

LTC2264CUJ-14#TRPBF概述

IC ADC 14BIT SER/PAR 40M 40-QFN

LTC2264CUJ-14#TRPBF规格参数

参数名称属性值
Brand NameLinear Technology
是否Rohs认证符合
厂商名称Linear ( ADI )
零件包装代码QFN
包装说明HVQCCN, LCC40,.24SQ,20
针数40
制造商包装代码UJ
Reach Compliance Codecompliant
ECCN代码3A991.C.3
最大模拟输入电压2 V
最小模拟输入电压-2 V
转换器类型ADC, PROPRIETARY METHOD
JESD-30 代码S-PQCC-N40
JESD-609代码e3
长度6 mm
最大线性误差 (EL)0.0183%
湿度敏感等级1
模拟输入通道数量2
位数14
功能数量1
端子数量40
最高工作温度70 °C
最低工作温度
输出位码OFFSET BINARY, 2\'S COMPLEMENT BINARY
输出格式SERIAL
封装主体材料PLASTIC/EPOXY
封装代码HVQCCN
封装等效代码LCC40,.24SQ,20
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)NOT SPECIFIED
电源1.8 V
认证状态Not Qualified
采样速率40 MHz
采样并保持/跟踪并保持SAMPLE
座面最大高度0.8 mm
标称供电电压1.8 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Matte Tin (Sn)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度6 mm

文档预览

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LTC2265-14/
LTC2264-14/LTC2263-14
14-Bit, 65Msps/40Msps/
25Msps Low Power Dual ADCs
FEATURES
n
n
n
n
n
n
n
n
n
n
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DESCRIPTION
The LTC
®
2265-14/LTC2264-14/LTC2263-14 are 2-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.7dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
2-Channel Simultaneous Sampling ADC
73.7dB SNR
90dB SFDR
Low Power: 171mW/113mW/94mW Total
85mW/56mW/47mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
n
n
n
n
n
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Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V
DD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
1.8V
OV
DD
OUT1A
OUT1B
AMPLITUDE (dBFS)
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226514 TA01
LTC2265-14, 65Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
–30
SERIALIZED
LVDS
OUTPUTS
–40
–50
–60
–70
–80
+
S/H
+
S/H
14-BIT
ADC CORE
14-BIT
ADC CORE
PLL
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
226514
TA02
22654314fb
1

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