or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
tn1257_01.3
PCB Layout Recommendations
for Leaded Packages
Perimeter Land Pad and Trace Design
In several published QFN tests, trace cracking was observed during board-level drop and bend tests. The reported
trace cracking usually occurred at the edge of the solder mask opening around the metal pad. To avoid this failure
mode, widen the trace under the solder mask edge so that it is wider than the remainder of the trace as shown in
Figure 1. Depending on the reliability requirements, the wider part of the trace might need to be as wide as 50 to
75% of the metal pad width.
Figure 1. Wider Trace Under Solder Mask Edge to Avoid Trace
Avoid if possible
A
B
Preferred, where
B > 50% A
Non-solder mask defined (NSMD) pads are recommended for dual-row QFN packages, because the copper etch-
ing process has tighter control than the solder masking process and improves the reliability of the solder joints.
Stencil Design for Perimeter Land Pads
For reliable solder joints on dual-row QFN packages, pay extra attention because of the small land surface area
and the sole reliance on printed solder paste on the PCB surface. Special considerations are needed in stencil
design and paste printing for both perimeter lands. Because the surface mount process varies from company to
company, careful process development is recommended. The following section provides some guidelines for sten-
cil design based on industry experience.
The optimum and reliable solder joints on the perimeter pads have about 50 to 70 ?m (2 to 3 mils) standoff height.
Tightly control the stencil aperture tolerance because these tolerances can effectively reduce the aperture size.
Area ratios of 0.66 and aspect ratios of 1.5 were never exceeded. The land pattern on the PCB should be 1:1 to the
land pads on QFN package.
Stencil thickness of 0.125 mm is recommended for 0.5 mm dual-row QFN packages. A laser-cut stainless steel
stencil with electro-polished trapezoidal walls is recommended to improve the paste release. Lattice recommends
that no-clean, Type 3 or Type 4 paste be used for mounting QFN packages. Nitrogen purge is also recommended
during reflow.
2
PCB Layout Recommendations
for Leaded Packages
Reflow Profile
Reflow profile and peak temperature have a strong influence on void formation. Lattice strongly recommends that
users follow the profile recommendation of the paste suppliers, since this is specific to the requirements of the flux
formation. However, the following profile, as shown in Figure 2, serves as a general reference for Lattice QFN
devices.
Figure 2. Typical Pb-Free Solder Flow
Wetting Time
10 - 20 seconds
260
255
217
Temperature (
o
C)
187
Preheat
120 seconds Max
Ramp
3 C/second Max.
Flux Activation/
Dryout
93
Cooling
6 C/second Max.
˚
˚
200
0
0
20
40
60
80
100
120
140
160
180
220
240
260
Time (seconds)
QFP and QFN Board Layout Recommendations
Lattice Semiconductor provides pre-designed layout examples for the various package options as listed in Table 2.
Some package layout examples provide different options depending on design and cost goals. For instance, layout
example includes all the programmable I/O pins but requires more total layers. An alternate layout uses fewer lay-
ers but provides few user I/O pins.
Table 2. Package Layout Example Summary
Package Pitch
Code
(mm)
QN84
VQ100
TQ144
0.50
0.50
0.50
iCE40
Family
Offerings
LP
HX
HX
Max.
I/Os
67
72
107
SMD/
Total Signal
NSMD Layers Layers
NSMD
NSMD
NSMD
1
4
4
1
1
1
Pad Size
(mm)
0.4 x 0.22
0.30
0.30 x 1.6
Solder Mask
(mm)
0.502 x 0.322
0.452
0.452 x 1.75
Via
Drill
(mil)
N/A
5
24
Via
Size
(mil)
N/A
10
12
Trace Trace
Width Space
(mil)
(mil)
4
5
8
3.5
5
8
All the examples assume that each I/O bank and the SPI bank each uses a different I/O voltage. In the layout
examples for a reduced number of layers, all the mandatory pins connections are routed out, including connections
such as the VPP_2V5 and the SPI connections. The PLL pins are also routed out on the packages that support
PLLs.
Free Allegro Viewer
If you do not already have a PCB board design software package but would like to view the files, simply download
and install the free Allegro viewer software available from Cadence.
Free Cadence Allegro Physical Viewer Downloads
www.cadence.com/products/pcb/Pages/downloads.aspx
3
PCB Layout Recommendations
for Leaded Packages
QN84 Quad-Flat No Lead Package
Leadless Quad Flat Pack (QFN) packages are plastic-encapsulated with a copper lead frame substrate, providing a
robust, low-cost solution for small form factor applications such as mobile handsets and other battery operated
consumer products. Dual-row QFN packages have interstitial, staggered contacts. The inner row is offset 0.5 mm,
resulting in a compact design that does not exceed the surface mount technology (SMT) capability of a typical 0.5
mm pitch surface-mount process.
For applications that require 67 PIO pins or less and a few board layers, the QN84 package uses somewhat
aggressive layout rules, as shown in Table 4. The single layer is shown in Figure 3.
The underside metal die paddle thermal pad is at Ground potential. It is designed to remove heat from the package
and enhance electrical performance. Although the low-power iCE40 mobile FPGA family generates little heat, the
extra ground connection enhances overall signal integrity.
Instead of one solid solder pad for the die paddle, multiple smaller openings in the solder paste stencil are used, as
shown in Table 3. This technique helps reduce voids, splattering, and solder balling).
Table 3. Solder Stencil Patterns for Thermal Pad
Stencil Pattern
Dimensions
Solder Paste Coverage
1.5 mm diameter circles at
1.6 mm pitch
37%
1.35 x 1.35 mm squares at
1.65 mm pitch
68%
For additional information on the QN84 package, see the application note AN016
Dual-Row QFN Package Assem-
bly and PCB Layout Guidelines.
Table 4. QN84, Single-Layer Layout Dimensions
Specification
Layers
Pad Size
Pad Solder Mask
Via Size (Drill)
Via Size (Pad)
Trace Width
Trace Spacing
0.4 x 0.22 mm
0.502 x 0.322 mm
None required
None required
0.1016 mm
0.889 mm
Dimension
1
15.748 x 8.6614 mils
19.7638 x 8.6614 mils
None required
None required
4 mils
3.5 mils
4
PCB Layout Recommendations
for Leaded Packages
Figure 3. QN84 Layout
For multilayer routing, Figure 4 shows the suggested board layout for the QN84 package on a top layer of a printed
circuit board, assuming NSMD solder mask rules. The labeled dimensions are listed in Table 5. Figure 5 shows the
suggested layout if pads are connected on inner layers.
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
