Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Measured from the time Vdd reaches its rated minimum value
No load condition, Vdd = 2.5V, 2.8V or 3.3V
No load condition, Vdd = 1.8V
Vdd = 2.5V, 2.8V or 3.3V, OE = GND, output is Weakly Pulled Down
Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down
Vdd = 2.5V, 2.8V or 3.3V, ST = GND, output is Weakly Pulled Down
Vdd = 1.8 V. ST = GND, output is Weakly Pulled Down
Condition
156.250000, 156.253906
156.257800, 156.257812
156.261718
-10
-20
-25
-50
–
–
–
–
–
–
1.8
2.5
2.8
3.3
31
29
–
–
–
–
–
1.2
2.2
3.4
–
–
–
–
100
–
7
–
6
1.5
2
0.25
–
–
+10
+20
+25
+50
+70
+85
1.89
2.75
3.08
3.63
33
31
31
30
70
10
55
2
–
–
–
10%
–
30%
250
–
10
150
10
2
3
0.3
+1.5
+5
Frequency Stability
F_stab
Inclusive of Initial tolerance at 25 °C, and variations over
operating temperature, rated power supply voltage and load
Operating Temperature Range
Supply Voltage
T_use
Vdd
-20
-40
1.71
2.25
2.52
2.97
Extended Commercial
Industrial
Supply voltages between 2.5V and 3.3V can be supported.
Contact
SiTime
for additional information.
Current Consumption
OE Disable Current
Standby Current
Duty Cycle
Rise/Fall Time
Idd
I_OD
I_std
DC
Tr, Tf
–
–
–
–
–
–
45
–
–
–
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Startup Time
OE Enable/Disable Time
Resume Time
RMS Period Jitter
RMS Phase Jitter (random)
First year Aging
10-year Aging
VOH
VOL
VIH
VIL
Z_in
T_start
T_oe
T_resume
T_jitt
T_phj
F_aging
90%
–
70%
–
–
2
–
–
–
–
–
–
-1.5
-5
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. Contact
SiTime
for custom drive strength to drive higher or multiple load, or SoftEdge™ option for EMI reduction.
SiTime Corporation
Rev. 1.11
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised March 4, 2013
SiT8256
0.3 ps Jitter Oscillator for Networking
The Smart Timing Choice
The Smart Timing Choice
Pin Configuration
Pin
Symbol
Output
Enable
1
OE/ ST
Standby
2
3
4
GND
OUT
VDD
Power
Output
Power
[3]
Functionality
H or Open : specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[3]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Electrical ground
Oscillator output
Power supply voltage
GND
2
Top View
OE/ST
1
4
VDD
3
OUT
Note:
3. A pull-up resistor of <10 kΩ between OE/ ST pin and Vdd is recommended in high noise environment
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050
5032
3225
2520
JA, 4 Layer Board
(°C/W)
191
97
109
117
JA, 2 Layer Board
(°C/W)
263
199
212
222
JC, Bottom
(°C/W)
30
24
27
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.11
Page 2 of 5
www.sitime.com
SiT8256
0.3 ps Jitter Oscillator for Networking
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
Vdd
Vout
Test
Point
tr
4
Power
Supply
0.1µF
3
tf
90% Vdd
1
2
15pF
(including probe
and fixture
capacitance)
50%
10% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
OE/ST Function
Vdd
1k
Figure 1. Test Circuit
Figure 2. Waveform
Notes:
4. Duty Cycle is computed as Duty Cycle = TH/Period.
5. SiT8256 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact
SiTime.
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
NO Glitch first cycle
ST Voltage
50% Vdd
T_resume
CLK Output
T_start
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 3. Startup Timing (OE/ST Mode)
u
Vdd
50% Vdd
T_OE
CLK Output
Figure 4. Standby Resume Timing (ST Mode Only)
OE Voltage
Vdd
OE Voltage
50% Vdd
CLK Output
T_OE
HZ
T_OE: Time to re-enable the clock output
T_OE: Time to put the output drive in High Z mode
Figure 5. OE Enable Timing (OE Mode Only)
Figure 6. OE Disable Timing (OE Mode Only)
Notes:
6. SiT8256 supports no runt pulses and no glitches during startup or resume.
7. SiT8256 supports gated output which is accurate within rated frequency stability from the first cycle.
Rev. 1.11
Page 3 of 5
www.sitime.com
SiT8256
0.3 ps Jitter Oscillator for Networking
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[8]
2.7 x 2.4 x 0.75 mm (100% compatible with 2.5 x 2. 0 mm footprint)
Recommended Land Pattern (Unit: mm)
[9]
2.7 ± 0.05
1.00
1.9
2.4 ± 0.05
0.75 ± 0.05
1.1
3.2 x 2.5 x 0.75 mm
3.2 ± 0.05
#4
#3
#3
2.1
#4
2.2
2.5 ± 0.05
0.9
0.7
YXXXX
#1
#2
1.9
#2
#1
0.75 ± 0.05
0.9
1
.4
5.0 x 3.2 x 0.75 mm
5.0 ± 0.05
#4
#3
#3
2.54
2.39
#4
3.2 ± 0.05
0.8
1.1
YXXXX
#1
#2
2.2
0.75 ± 0.05
#2
#1
1.15
1.5
7.0 x 5.0 x 0.90 mm
7.0 ± 0.05
5.08
5.08
5.0 ± 0.05
2.6
YXXXX
1.1
3.81
1.6
2.2
1.2
1.0
0.85
1.5
YXXXX
1.25
0.50
Notes:
8. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
9. A capacitor of value 0.1 µF between Vdd and GND is recommended.
Rev. 1.11
0.90 ± 0.10
1.4
Page 4 of 5
2.0
www.sitime.com
SiT8256
0.3 ps Jitter Oscillator for Networking
The Smart Timing Choice
The Smart Timing Choice
Ordering Information
SiT8256AC-23-25E -156.000000T
Part Family
“SiT8256”
Revision Letter
“A” is the silicon revision
Temperature Range
“C” Ext. Commercial, -20 to 70ºC
“I” Industrial, -40 to 85ºC
Output Driver Strength
[10]
“–” Default
Package
“G”
“2”
“3”
“8”
2.5 x 2.0
3.2 x 2.5
5.0 x 3.2
7.0 x 5.0
Packaging
“T”: Tape & Reel, 3K reel
“Y”: Tape & Reel, 1K reel
Blank for Bulk
Frequency
156.250000 MHz
156.253906 MHz
156.257800 MHz
156.257812 MHz
156.261718 MHz
Feature Pin
“E” for Output Enable
“S” for Standby
Voltage Supply
“18” for 1.8V ±5%
“25” for 2.5V ±10%
“28” for 2.8V ±10%
“33” for 3.3V ±10%
Frequency Tolerance
“F” for ±10 PPM
“1” for ±20 PPM
“2” for ±25 PPM
“3” for ±50 PPM
Note:
10. Contact
SiTime
for custom drive strength to drive higher or multiple load, or SoftEdge™ option for EMI reduction.
Additional Information
Document
Manufacturing Notes
Qualification Reports
Performance Reports
Termination Techniques
Layout Techniques
Description
Tape & Reel dimension, reflow profile and other manufacturing
Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii)
unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper
installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
Disclaimer:
SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by
operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or
usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by
SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved
or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below.
CRITICAL USE EXCLUSION POLICY
BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES
OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE.
SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products
does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the
sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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