PD 9.1407
PRELIMINARY
IRFIZ48N
HEXFET
®
Power MOSFET
D
l
l
l
l
l
Advanced Process Technology
Isolated Package
High Voltage Isolation = 2.5KVRMS
Sink to Lead Creepage Dist. = 4.8mm
Fully Avalanche Rated
U
G
V
DSS
= 55V
R
DS(on)
= 0.016Ω
I
D
= 36A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve extremely
low on-resistance per silicon area. This benefit, combined
with the fast switching speed and ruggedized device
design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient and
reliable device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
36
25
210
42
0.28
± 20
270
32
4.2
5.6
-55 to + 175
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient
Typ.
–––
–––
Max.
3.6
65
Units
°C/W
IRFIZ48N
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
Min. Typ. Max. Units
Conditions
55
––– –––
V
V
GS
= 0V, I
D
= 250µA
––– 0.052 ––– V/°C Reference to 25°C, I
D
= 1mA
––– ––– 0.016
Ω
V
GS
= 10V, I
D
= 22A
2.0
––– 4.0
V
V
DS
= V
GS
, I
D
= 250µA
22
––– –––
S
V
DS
= 25V, I
D
= 32A
––– ––– 25
V
DS
= 55V, V
GS
= 0V
µA
––– ––– 250
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
––– ––– 100
V
GS
= 20V
nA
––– ––– -100
V
GS
= -20V
––– ––– 89
I
D
= 32A
––– ––– 20
nC V
DS
= 44V
––– ––– 39
V
GS
= 10V, See Fig. 6 and 13
–––
11
–––
V
DD
= 28V
–––
78
–––
I
D
= 32A
ns
–––
32 –––
R
G
= 5.1Ω
–––
48 –––
R
D
= 0.85Ω, See Fig. 10
Between lead,
4.5 –––
–––
6mm (0.25in.)
nH
G
from package
–––
7.5 –––
and center of die contact
––– 1900 –––
V
GS
= 0V
–––
620 –––
V
DS
= 25V
pF
––– 270 –––
ƒ = 1.0MHz, See Fig. 5
–––
12 –––
ƒ = 1.0MHz
D
S
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
–––
–––
–––
–––
–––
–––
94
360
36
A
210
1.3
140
540
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 22A, V
GS
= 0V
T
J
= 25°C, I
F
= 32A
di/dt = 100A/µs
D
S
Q
Repetitive rating; pulse width limited by
SD
≤
32A,
R
V
S
I
max. junction temperature. ( See fig. 11 )
DD
= 25V, starting T
J
= 25°C, L = 530µH
R
G
= 25Ω, I
AS
= 32A. (See Figure 12)
T
Pulse width
≤
300µs; duty cycle
≤
2%.
U
t=60s, ƒ=60Hz
Uses IRFZ48N data and test conditions
di/dt
≤
250A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
IRFIZ48N
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
1000
I , Drain-to-Source Current (A)
D
I , Drain-to-Source Current (A)
D
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
10
10
4.5V
1
1
4.5V
0.1
0.1
20µs PULSE WIDTH
T
C
= 25°C
10
A
0.1
0.1
1
20µs PULSE WIDTH
T
C
= 175°C
10
100
A
1
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics,
T
J
= 25
o
C
Fig 2.
Typical Output Characteristics,
T
J
= 175
o
C
1000
2.5
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 53A
I
D
, Drain-to-Source Current (A)
2.0
100
T
J
= 175°C
10
1.5
T
J
= 25°C
1.0
1
0.5
0.1
4
5
6
7
V
DS
= 25V
20µs PULSE WIDTH
8
9
10
A
0.0
-60 -40 -20
V
GS
= 10V
0
20
40
60
A
8 0 100 120 140 160 180
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRFIZ48N
4000
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
20
I
D
= 32A
V
DS
44V
=
V
DS
28V
=
16
C, Capacitance (pF)
3000
C
iss
12
2000
C
oss
8
GS
1000
C
rss
V
4
0
1
10
100
A
0
0
20
40
FOR TEST CIRCUIT
SEE FIGURE 13
60
80
100
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
I
D
, Drain Current (A)
T
J
= 175°C
10
100
10µs
T
J
= 25°C
100µs
10
1ms
1
10ms
0.1
0.2
0.6
1.0
1.4
1.8
V
GS
= 0V
2.2
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
100
A
2.6
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating
Area
IRFIZ48N
V
DS
40
R
D
V
GS
R
G
D.U.T.
+
I
D
, Drain Current (Amps)
-
V
DD
30
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
20
Fig 10a.
Switching Time Test Circuit
10
V
DS
90%
0
25
50
75
100
125
150
A
175
T
C
, Case Temperature (°C)
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10
Fig 10b.
Switching Time Waveforms
Thermal Response (Z
thJC
)
D = 0.50
1
0.20
0.10
0.05
P
DM
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
t
1
t2
1
/t
2
0.01
0.00001
2. Peak TJ = PDM x Z thJC + T C
A
10
0.0001
0.001
0.01
0.1
1
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
FPGA/CPLD
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