February 1996
NDS9953A
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
-2.9A, -30V. R
DS(ON)
= 0.13
Ω
@ V
GS
= -10V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
________________________________________________________________________________
5
4
3
2
1
6
7
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
A
= 25°C unless otherwise noted
NDS9953A
-30
± 20
(Note 1a)
Units
V
V
A
± 2.9
± 10
2
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
1.6
1
0.9
-55 to 150
°C
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS9953A.SAM
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Parameter
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
Conditions
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -24 V, V
GS
= 0 V
T
J
= 55°C
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
= 125°C
V
GS
= -10 V, I
D
= -1.0 A
T
J
= 125°C
V
GS
= -4.5 V, I
D
= -0.5 A
T
J
= 125°C
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -10 V,
I
D
= -2.9 A, V
GS
= -10 V
V
DD
= -10 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
Ω
V
GS
= -10 V, V
DS
= -5 V
V
GS
= -4.5 V, V
DS
= -5 V
V
DS
= -15 V, I
D
= -2.9 A
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
350
260
100
9
21
21
8
10
1.6
3.4
40
40
90
50
25
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
-10
-1.5
4
S
-1
-0.85
-1.6
-1.25
0.11
0.15
0.17
0.24
Min
-30
-2
-25
100
-100
-2.8
-2.5
0.13
0.21
0.2
0.32
A
Typ
Max
Units
V
µA
µA
nA
nA
V
OFF CHARACTERISTICS
ON CHARACTERISTICS
(Note 2)
Ω
SWITCHING CHARACTERISTICS
(Note 2)
NDS9953A.SAM
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
t
rr
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
-1.2
Units
A
V
ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= -1.25 A
(Note 2)
-0.8
-1.3
100
V
GS
= 0 V, I
F
= -1.25 A, dI
F
/dt = 100 A/µs
P
D
(
t
) =
T
J
−
T
A
R
θ
J A
t
)
(
=
T
J
−
T
A
R
θ
J C
R
θ
CA
t
)
+
(
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 0.5 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.02 in
2
pad of 2oz cpper.
c. 135
o
C/W when mounted on a 0.003 in
2
pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9953A.SAM
Typical Electrical Characteristics
-20
V
GS
= -10V
, DRAIN-SOURCE CURRENT (A)
-15
3
-8.0
DRAIN-SOURCE ON-RESISTANCE
-7.0
R
DS(on)
, NORMALIZED
V
GS
= -3.5V
2.5
-4.0
-4.5
-5.0
-6.0
-5.5
-5.0
2
-5.5
-6.0
-10
-4.5
-4.0
-5
1.5
-3.5
-3.0
1
-7.0
-8.0
-10
I
0
D
0
-1
V
DS
-2
-3
, DRAIN-SOURCE VOLTAGE (V)
-4
-5
0.5
0
-3
-6
-9
I
D
, DRAIN CURRENT (A)
-12
-15
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
2
DRAIN-SOURCE ON-RESISTANCE
1.4
R
DS(ON)
, NORMALIZED
V
G S
= -10V
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= -2.9A
V
GS
= -10V
TJ = 125°C
1.5
1.2
1
25°C
1
0.8
-55°C
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.5
0
-3
-6
-9
I
D
, DRAIN CURRENT (A)
-12
-15
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
-10
GATE-SOURCE THRESHOLD VOLTAGE
1.2
V
DS
= -10V
-8
I
D
, DRAIN CURRENT (A)
TJ = -55°C
25°C
125°C
V
th
, NORMALIZED
1.1
V
DS
= V
GS
I
D
= -250µA
-6
1
-4
0.9
-2
0.8
0
-1
-2
-3
-4
-5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-6
0.7
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDS9953A.SAM
Typical Electrical Characteristics
(continued)
1.1
DRAIN-SOURCE BREAKDOWN VOLTAGE
I
D
= -250µA
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
-I
S
, REVERSE DRAIN CURRENT (A)
10
5
V
GS
= 0V
BV
DSS
, NORMALIZED
1
0.5
T = 125°C
J
25°C
-55°C
0.1
0.01
0.001
0.2
0.4
0.6
0.8
1
1.2
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature
.
1000
800
10
-V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= -2.9A
8
V
DS
= -10V
-20V
-15V
500
CAPACITANCE (pF)
C iss
300
200
6
C oss
4
100
f = 1 MHz
V
GS
= 0V
C rss
2
50
0.1
0.2
0.5
1
2
5
10
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
0
0
2
4
6
8
Q
g
, GATE CHARGE (nC)
10
12
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristic.
6
V
DS
= -15V
, TRANSCONDUCTANCE (SIEMENS)
5
TJ = -55°C
25°C
4
125°C
3
2
1
g
0
0
FS
-2
I
D
-4
-6
, DRAIN CURRENT (A)
-8
-10
Figure 11. Transconductance Variation with Drain
Current and Temperature.
NDS9953A.SAM
FPGA/CPLD
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