March 1996
NDC652P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast high-side switching,
and low in-line power loss are needed in a very small
outline surface mount package.
Features
-2.4A, -30V. R
DS(ON)
= 0.18
Ω
@ V
GS
= -4.5V
R
DS(ON)
= 0.11
Ω
@ V
GS
= -10V.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
T
A
= 25°C unless otherwise noted
NDC652P
-30
-20
-2.4
-10
(Note 1a)
(Note 1b)
(Note 1c)
Units
V
V
A
1.6
1
0.8
-55 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a
)
(Note 1)
78
30
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -24 V, V
GS
= 0 V
T
J
= 55 C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
= 125
o
C
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= -2.4 A
T
J
= 125
o
C
V
GS
= -10 V, I
D
= -3.1 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= -4.5 V, V
DS
= -5 V
V
DS
= -10 V, I
D
= -2.4 A
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
-5
3
-1
-0.7
-1.5
-1.2
0.16
0.22
0.09
o
-30
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
-3
-2.2
0.18
0.36
0.11
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
290
180
60
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -15 V,
I
D
= -2.4 A, V
GS
= -10 V
V
DD
= -15 V, I
D
= -1 A,
V
GEN
= -4.5 V, R
GEN
= 6
Ω
13
26
22
19
10.5
1.5
3.3
20
35
30
30
20
ns
ns
ns
ns
nC
nC
nC
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Continuous Source Diode Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.8
-1.3
-1.2
A
V
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.01 in
2
pad of 2oz cpper.
c. 156
o
C/W when mounted on a 0.003 in
2
pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC652P Rev. D1
Typical Electrical Characteristics
-10
2.5
V
GS
I
D
, DRAIN-SOURCE CURRENT (A)
-8
= -10V
DRAIN-SOURCE ON-RESISTANCE
-7.0 -6.0 -5.5
-5.0
-4.5
R
DS(ON)
, NORMALIZED
V
GS
= -3.0V
2
-3.5
-4.0
-6
-4.0
1.5
-4.5
-5.0
-4
-3.5
1
-2
-3.0
-2.5
-5.5
-6.0
-7.0
-10
0
-2
-4
-6
I
D
, DRAIN CURRENT (A)
-8
-10
0
0
-0.5
V
DS
-1
-1.5
-2
-2.5
, DRAIN-SOURCE VOLTAGE (V)
-3
0.5
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
1.6
2.5
DRAIN-SOURCE ON-RESISTANCE
1.4
V
GS
= -4.5V
R
DS(on)
NORMALIZED
,
DRAIN-SOURCE ON-RESISTANCE
I
D
= -2.4A
V
GS
= -4.5 V
2
R
DS(ON)
, NORMALIZED
1.2
T J = 125°C
1.5
1
25°C
0.8
1
-55°C
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.5
0
-2
-4
-6
I
D
, DRAIN CURRENT (A)
-8
-10
Figure 3. On-Resistance Variation
with Temperature
Figure 4. On-Resistance Variation
with Drain Current and Temperature
-10
1.2
T J = -55°C
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= - 10V
-8
125°C
1.1
V
DS
= V
I
D
GS
= -250µA
I
D
, DRAIN CURRENT (A)
-6
V
th
, NORMALIZED
25°C
1
0.9
-4
0.8
-2
0.7
0
-1
-2
-3
-4
-5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-6
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation
with Temperature
NDC652P Rev. D1
Typical Electrical Characteristics
(continued)
1.1
10
DRAIN-SOURCE BREAKDOWN VOLTAGE
I
D
= -250µA
-I
S
, REVERSE DRAIN CURRENT (A)
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
5
V
G S
= 0V
T J = 125°C
25°C
-55°C
1
BV
DSS
, NORMALIZED
0.1
0.01
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage Variation
with Temperature
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
1000
10
I
D
= -2.4A
-V
GS
, GATE-SOURCE VOLTAGE (V)
500
CAPACITANCE (pF)
8
V
DS
= -5V
-15V
-10V
C iss
C oss
200
6
4
100
f = 1 MHz
V
GS
= 0 V
C rss
2
50
0.1
0.2
0.5
1
2
5
10
-V
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
0
0
2
4
6
8
10
12
Q
g
, GATE CHARGE (nC)
Figure 9. Capacitance Characteristics
Figure 10. Gate Charge Characteristics
-V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
90%
G
DUT
S
V
IN
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
NDC652P Rev. D1
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