ST7580
FSK, PSK multi-mode power line networking system-on-chip
Datasheet
-
production data
Fully integrated single-ended power amplifier
for line driving
– Up to 1 A RMS, 14 V p-p output
– Configurable active filtering topology
– Very high linearity
– Embedded temperature sensor
– Current control feature
8 to 18 V power amplifier supply
3.3 V or 5 V digital I/O supply
Zero crossing detection
Suitable for EN50065, FCC part 15 and ARIB
compliant applications
Communication carrier frequency
programmable up to 250 kHz
VFQFPN48 7x7x1.0 48L exposed pad
package
-40 °C to +105 °C temperature range
Features
Fully integrated narrow-band power line
networking system-on-chip
High-performing PHY processor with
embedded turnkey firmware featuring:
– B-FSK modulation up to 9.6 kbps
– B-PSK, Q-PSK, 8-PSK modulations up to
28.8 kbps
– Dual channel operation mode
– Convolutional error correction coding
– Signal-to-noise ratio estimation
– B-PSK with PNA mode against impulsive
noise
Protocol engine embedding turnkey
communication protocol
– Framing service
– Error detection
– Sniffer functionality
Host controller UART interface up to 57.6 kbps
AES-128 based authentication and
confidentiality services
Fully integrated analog front-end:
– ADC and DAC
– Digital transmission level control
– PGA with automatic gain control
– High sensitivity receiver
Applications
Smart metering applications
Street lighting control
Command and control networking
Description
The ST7580 is a flexible power line networking
system-on-chip combining a high performing PHY
processor core and a protocol controller with a
fully integrated analog front-end (AFE) and line
driver for a scalable future-proof, cost effective,
single chip, narrow-band power line
communication solution.
Table 1. Device summary
Order codes
ST7580
ST7580TR
Package
VFQFPN48
Packaging
Tube
Tape and reel
May 2016
This is information on a product in full production.
DocID022644 Rev 2
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Contents
ST7580
Contents
1
2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Analog front-end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
5.5
5.6
Reception path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmission path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current and voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal shutdown and temperature control . . . . . . . . . . . . . . . . . . . . . . . 18
Zero crossing comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
8
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9
Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1
PSK modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1.1
9.1.2
PSK modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PSK physical frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Contents
9.2
FSK modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.1
9.2.2
9.2.3
FSK options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FSK physical frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FSK settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.3
Channel and modulation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Data link layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.1
10.2
10.3
Data link frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Error detection and sniffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Security services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1
VFQFPN48 (7 x 7 x 1.0 mm) package information . . . . . . . . . . . . . . . . . 30
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Device overview
ST7580
1
Device overview
Made using multi-power technology with state-of-the-art VLSI CMOS lithography, the
ST7580 is based on dual digital core architecture (a PHY processor engine and a protocol
controller core) to guarantee outstanding communication performance with a high level of
flexibility for either open standards or customized implementations.
A HW 128-bit AES encryption block with customizable key management is available on chip
when secure communication is requested.
The on-chip analog front-end featuring analog to digital and digital to analog conversion,
automatic gain control, plus the integrated power amplifier delivering up to 1 A RMS output
current makes the ST7580 a unique system-on-chip for power line communication.
Line coupling network design is also simplified, leading to a very low cost BOM.
Robust and performing operations are guaranteed while keeping power consumption and
signal distortion levels very low; this makes the ST7580 an ideal platform for the most
stringent application requirements and regulatory standards compliance.
Figure 1. Block diagram
PA_IN+
PA_IN-
CL
PA_OUT
+
-
Thermal
Management
Output Current
Control
ON-CHIP
Memories
T_REQ
Line Driver
ON-CHIP
Memories
SPI0/UART
RXD
TXD
128bit
AES
TX_OUT
DAC
GAIN
CTRL
BPF
TX AFE
DDS
Protocol
Controller
PHY processor
WATCHDOG
TIMERS
BR1
BR0
RX_IN
PGA
ADC
BPF
PL_RX_ON
PL_TX_ON
RX AFE
VCC
(8-18V)
VDDIO
(5 / 3.3V)
Power Management
Zero Crossing
Detection
Clock Management
VCCA
(5V)
ZC_IN
VDD
(1.8V)
VDD_PLL
(1.8V)
XIN
XOUT
AM02502v1
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ST7580
Pin connection
2
Pin connection
Figure 2. Pinout top view
RESERVED5
RESERVED4
RESERVED3
RESERVED2
RESERVED1
PL_RX_ON
PL_TX_ON
48 47 46 45 44 43 42 41 40 39 38 37
T_REQ
GND
VDD
BR0
BR1
TXD
RXD
VDDIO
TRSTN
TMS
GND
TCK
TDO
TDI
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
CL_SEL
VSSA
VDDIO
GND
NC
RESERVED0
NC
NC
VDDIO
VDD_REG_1V8
PA_OUT
VSS
RESETN 10
VDD 11
XIN 12
13 14 15 16 17 18 19 20 21 22 23 24
TX_OUT
PA_IN+
PA_IN-
XOUT
VCCA
VSSA
ZC_IN
RX_IN
CL
VDD_PLL
GND
VCC
AM02503v1
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