PMWD19UN
Dual
µTrenchMOS™
ultra low level FET
Rev. 01 — 20 December 2002
M3D647
Product data
1. Product profile
1.1 Description
Dual N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PMWD19UN in SOT530-1 (TSSOP8).
1.2 Features
s
Surface mounting package
s
Very low threshold
s
Low profile
s
Fast switching.
1.3 Applications
s
Portable appliances
s
Battery management
s
PCMCIA cards
s
Load switching.
1.4 Quick reference data
s
V
DS
≤
30 V
s
P
tot
≤
2.3 W
s
I
D
≤
5.6 A
s
R
DSon
≤
23 mΩ.
2. Pinning information
Table 1:
Pin
1
2,3
4
5
6,7
8
Pinning - SOT530-1, simplified outline and symbol
Description
drain1 (d1)
source1 (s1)
gate1 (g1)
gate2 (g2)
source2 (s2)
drain2 (d2)
1
Top view
4
MBK885
Simplified outline
8
5
Symbol
d1
d2
s1
g1
s2
g2
MSD901
SOT530-1
Philips Semiconductors
PMWD19UN
Dual
µTrenchMOS™
ultra low level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage
gate-source voltage
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
V
GS
= 4.5 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 4.5 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
30
30
±10
5.6
3.4
20
2.3
+150
+150
2
7
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 10833
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 20 December 2002
2 of 12
Philips Semiconductors
PMWD19UN
Dual
µTrenchMOS™
ultra low level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp (
°
C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
V
GS
≥
4.5 V
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
10
1 ms
10 ms
1
100 ms
DC
10-1
1s
003aaa358
Limit RDSon = VDS/ID
tp = 10 µs
10-2
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10833
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 20 December 2002
3 of 12
Philips Semiconductors
PMWD19UN
Dual
µTrenchMOS™
ultra low level FET
4. Thermal characteristics
Table 3:
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
minimum footprint;
mounted on printed-circuit board
Min Typ Max
-
-
55
70
100 -
Unit
K/W
K/W
thermal resistance from junction to solder point
thermal resistance from junction to ambient
Symbol Parameter
4.1 Transient thermal impedance
102
Zth(j-sp)
(K/W)
003aaa275
δ
= 0.5
0.2
10
0.1
0.05
0.02
1
single pulse
P
δ
=
tp
T
tp
T
10-
1
10-4
10-
3
10-
2
10-
1
1
10
tp (s)
t
10
2
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10833
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 20 December 2002
4 of 12
Philips Semiconductors
PMWD19UN
Dual
µTrenchMOS™
ultra low level FET
5. Characteristics
Table 4:
Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 1 mA; V
DS
= V
GS;
Figure 9
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 3.5 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 1.8 V; I
D
= 3.5 A;
Figure 7
V
GS
= 2.5 V; I
D
= 3.5 A;
Figure 7
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 4 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 4 A; dI
S
/dt =
−100
A/µs; V
R
= 30 V;
V
GS
= 0 V
V
DD
= 15 V; I
D
= 1 A; V
GS
= 4.5 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 10 V; f = 1 MHz;
Figure 11
I
D
= 5 A; V
DD
= 16 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
28
2.3
6.1
161
128
15
23
56
30
0.67
50
19
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
-
-
-
-
-
-
-
-
-
19
32
25
21
1
100
100
-
23
39
35
26
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
mΩ
30
27
0.45
-
-
0.7
-
-
-
V
V
V
Conditions
Min
Typ
Max
Unit
1478 -
Source-drain diode
9397 750 10833
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 20 December 2002
5 of 12
FPGA/CPLD
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