www.fairchildsemi.com
FAN6555
2A DDR Bus Termination Regulator
Features
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Can source and sink up to 2A continous, 3A peak
No heatsink required
Integrated Power MOSFETs
Generates termination voltages for DDR SDRAM
V
REF
input available for external voltage divider
Separate voltages for V
CCQ
and PV
DD
Buffered V
REF
output
V
OUT
of ±3% or less at 2A
Minimum external components
16-pin SOIC package
-40°C to +85°C operating temperature range
Shutdown for standby or suspend mode operation
Thermal Shutdown
≈
130ºC
Description
The FAN6555 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired out-
put voltage or termination voltage for DDR SDRAM mem-
ory. The FAN6555 can be implemented to produce regulated
output voltages in two different modes. In the default mode,
when the V
REF
pin is open, the FAN6555 output voltage is
50% of the voltage applied to V
CCQ
. The FAN6555 can also
be used to produce various user-defined voltages by forcing a
voltage on the VREF
IN
pin. In this case, the output voltage
follows the input VREF
IN
voltage. The switching regulator
is capable of sourcing or sinking up to 2A of current while
regulating an output V
TT
voltage to within 3% or less.
Transient output currents of ±3A can also be accommodated.
The FAN6555 can also be used in conjunction with series
termination resisitors to provide an excellent voltage source
for active termination schemes of high speed transmission
lines as those seen in high speed memory buses and distrib-
uted backplane designs.
Block Diagram
15
16
14
1
9
VDD
VDD
12
2
7
VCCQ
AVCC
VREFOUT
SHDN
PVDD1
PVDD2
VL1
(VOUT)
3
OSCILLATOR/
RAMP
GENERATOR
–
200kΩ
+
VREF BUFFER
VREFIN
11
200kΩ
AGND
13
+
–
–
R
+
ERROR AMP
RAMP
COMPARATOR
Q
S
Q
6
VL2
(VOUT)
VFB
10
8
DGND
4
PGND1
5
PGND2
REV. 1.1.3 8/4/03
FAN6555
PRODUCT SPECIFICATION
Pin Configuration
FAN6555
16-Pin SOIC (M16)
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
TOP VIEW
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
V
DD
PV
DD1
V
L1
P
GND1
P
GND2
V
L2
PV
DD2
D
GND
V
DD
V
FB
VREF
IN
SHDN
AGND
VREF
OUT
V
CCQ
AV
CC
Digital supply voltage
Voltage supply for internal power transistors
Output voltage/ inductor connection
Ground for output power transistors
Ground for output power transistors
Output voltage/inductor connection
Voltage supply for internal power transistors
Digital ground
Digital supply voltage
Input for external compensation feedback
Input for external reference voltage
Shutdown active low. CMOS input level
Ground for internal reference voltage divider
Reference voltage output
Voltage reference for internal voltage divider
Analog voltage supply
Function
2
REV. 1.1.3 8/4/03
PRODUCT SPECIFICATION
FAN6555
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
PV
DD
Voltage on Any Other Pin
Average Switch Current (I
AVG
)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance: Junction to Case (
θ
JC
)
Junction to Ambient (
θ
JA
)
Output Current, Source or Sink (peak)
Min.
GND – 0.3
Max.
4.5
V
IN
+ 0.3
2.0
150
150
300
30
88
3.0
Units
V
V
A
°C
°C
°C
°C/W
A
-65
Operating Conditions
Parameter
Temperature Range
PV
DD
Operating Range
V
CCQ
Operating Range
Min.
-40
2.0
1.4
Max.
+85
4.0
4.0
Units
°C
V
V
Electrical Characteristics
Unless otherwise specified, AV
CC
= V
DD
= PV
DD
= 3.3V ±10%, T
A
= Operating Temperature Range (Note 1)
Symbol
Parameter
Switching Regulator
Output Voltage, V
TT
V
TT
(See Figure 1)
Conditions
I
OUT
= 0,
V
REF
= open
Note 2
I
OUT
= ±2A,
V
REF
= open
T
A
= 25°C
Note 2
VREF
OUT
Internal Resistor Divider
I
OUT
= 0
Note 2
Note 2
Min.
V
CCQ
= 2.3V 1.12
V
CCQ
= 2.5V 1.22
V
CCQ
= 2.7V 1.32
V
CCQ
= 2.3V 1.09
V
CCQ
= 2.5V 1.19
V
CCQ
= 2.7V 1.28
Typ.
1.15
1.25
1.35
1.15
1.25
1.35
Max. Units
1.18
1.28
1.38
1.21
1.31
1.42
V
V
V
V
V
V
V
V
V
k
Ω
kHz
mV
µA
mA
mA
mA
mA
µA
mA
Z
IN
∆
V
OFFSET
Supply
I
Q
V
REF
Reference Pin Input
Impedance
Switching Frequency
Offset Voltage V
TT
– VREF
OUT
Quiescent Current
V
CCQ
= 2.3V 1.139 1.15 1.162
V
CCQ
= 2.5V 1.238 1.25 1.263
V
CCQ
= 2.7V 1.337 1.35 1.364
V
CCQ
= 0
100
650
AV
CC
= 2.5V No Load V
CCQ
= 2.5
I
OUT
= 0, no load
V
CCQ
= 2.5V
I
VCCQ
I
AVCC
I
AVCC
SD
I
VDD
I
VDD
SD
I
PVDD
–20
6
0.5
0.2
0.25
0.2
100
3
20
10
1.0
0.5
1.0
1.0
250
Buffer
I
REF
Output Current Capability
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. AV
CC
, PV
DD
= 3.3V ±10%
REV. 1.1.3 8/4/03
3
FAN6555
PRODUCT SPECIFICATION
Functional Description
The FAN6555 integrates two power MOSFETs that can be
used to source and sink 2A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less, depending on
the external components chosen. Separate voltage supply
inputs have been added to accommodate applications with
various power supplies for the databus and power buses.
VREF Input and Output
The VREF
IN
input can be used to force a voltage at the
outputs (Inputs section, above). The VREF
OUT
pin is an
output pin that is driven by a small output buffer to provide
the V
REF
signal to other devices in the system. The output
buffer is capable of driving several output loads. The output
buffer can handle 3mA.
Other Supply Voltages
Several inputs are provide for the supply voltages: PV
DD1
,
PV
DD2
, AV
CC
, and V
DD
.
The PV
DD1
and PV
DD2
provide the power supply to the
power MOSFETs. V
DD
provides the voltage supply to the
digital sections, while AV
CC
supplies the voltage for the
analog sections. Again, see the Applications section for
recommendations.
Outputs
The output voltage pins (V
L1
, V
L2
) are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output voltage
is determined by the V
CCQ
or VREF
IN
inputs.
Inputs
The input voltage pins (V
CCQ
or VREF
IN
) determine the
output voltages (V
L1
or V
L2
) . In the default mode, where
the VREF
IN
pin is floating, the output voltage is 50% of the
V
CCQ
input. V
CCQ
can be the reference voltage for the
databus.
Output voltage can also be selected by forcing a voltage at
the VREF
IN
pin. In this case, the output voltage follows the
voltage at the VREF
IN
input. Simple voltage dividers can be
used in this case to produce a wide variety of output voltages
between 0.7V and V
DD
–0.7V.
Feedback Input
The V
FB
pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
See Application section for recommendation.
2.5V TO 4V
R2 100Ω
R1 100Ω
C9 0.1µF
C8 0.1µF
R3
100kΩ
U1
FAN6555
TPI
1
2
VTT
C1
820µF
F2V
OS-CON
TO SDRAMS
L1 3.3µH C3 0.1µF
3
4
C2
0.1µF
C4 0.1µF
5
6
7
8
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
16
15
14
13
12
11
10
9
SHDN
VREFIN
VCCQ
VREFOUT
C5
470µF
R4 100kΩ
C7 1nF
GND
R5 1kΩ
GND
Figure 1.
4
REV. 1.1.3 8/4/03
PRODUCT SPECIFICATION
FAN6555
Applications
Using the FAN6555 for DDR Bus Termination
The circuit schematic in Figure 1 shows a recommended
approach for constructing a bus terminating solution for a
DDR bus. This circuit can be used in PC memory and Graph-
ics memory applications as shown in Figures 3 and 4. Note
that the FAN6555 can provide the voltage reference (V
REF
)
and terminating voltages (V
TT
). Using the layout
as shown in Figures 5, 6, and 7, and measuring the V
TT
performance using the test setup as described in Figure 8,
the FAN6555 delivered a V
TT
± 20mV for 1A to 2A loads
(see Figure 9). Table 1 provides a recommended parts list.
An alternate application circuit for the FAN6555 is shown in
Figure 2. The number of external components is reduced
compared to the circuit in Figure 1. This is achieved by
replacing four, 0.1µF bypass capacitors with one, low ESR,
10µF ceramic capacitor placed right next to U1. Two 100Ω
resistors are also eliminated. High value, surface-mount
MLC capacitors were not available when the original appli-
cation circuit (Figure 1) was developed. Both application
circuits offer the same electrical performance but the circuit
shown in Figure 2 has a reduced bill-of-materials. Table 2
shows the recommended parts list for the circuit of Figure 2.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination V
REF
& V
TT
requirements. The FAN6555 can be used for those
applications.
2.5V TO 4V
C5
470µF
U1
FAN6555
1
C3 10µF
VTT
C1
820µF
F2V
OS-CON
TO SDRAMS
L1 3.3µH
2
3
4
C2
0.1µF
5
6
7
8
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
16
15
14
13
12
11
10
9
R3
100kΩ
VCCQ
VREFOUT
SHDN
VREFIN
R1 100kΩ
C4 1nF
GND
R2 1kΩ
GND
Figure 2. Alternate Application Circuit
REV. 1.1.3 8/4/03
5
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