www.fairchildsemi.com
FAN5068
DDR-1/DDR-2 plus ACPI Regulator Combo
Features
• PWM regulator for VDDQ (2.5V or 1.8V)
• Linear LDO regulator generates VTT = VDDQ/2, 1.5A
Peak sink/source capability
• 1 independent programable ULDO controllers driving
external N-Channel MOSFET
• ACPI drive and control for 5V DUAL generation
• 3.3V Internal LDO for 3V-ALW generation
• 300kHz fixed frequency switching
• R
DS(ON)
current sensing or optional current sense resistor
for precision over-current detect
• Internal Synchronous Boot diode
• Power Good signal for all voltages
• Input Under-Voltage Lock-Out (UVLO)
• Thermal Shutdown
• Latched Multi-Fault Protection
• 24-pin 5x5mm MLP package
General Description
The FAN5068 DDR memory regulator combines a high-
efficiency PWM controller to generate the supply voltage,
VDDQ, and a linear regulator to generate VTT, the termina-
tion voltage. Synchronous rectification provides high-
efficiency over a wide range of load currents. Efficiency is
further enhanced by using the low-side MOSFET’s R
DS(ON)
to sense current instead of a series sense resistor.
In S3 mode, only the VDDQ switcher and the 3.3V regula-
tors remain on while the VTT and ULDO regulators are shut
off. To avoid "glitching" the VDDQ output during the transi-
tion from S3 to S0, the three linear regulators use the SS
capacitor to limit their slew rates, thereby limiting the surge
current from the VDDQ output. PGOOD becomes true in S0
only when all 3 regulators have achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on, while the
other regulators are powered down.
The VDDQ PWM regulator is a sampled current mode con-
trol with external compensation to achieve fast load transient
response and provide system design optimization.
The VTT regulator derives its reference and takes its power
from the VDDQ PWM regulator output using a precision
internal voltage divider to set its output at 1/2 of VDDQ. The
VTT termination regulator is capable of sourcing or sinking
at least 1.5A peak current.
Applications
• DDR-1/DDR-2 VDDQ and VTT voltage generation with
ACPI support
• Desktop PC's
• Servers
REV. 1.0.1 9/9/04
PRODUCT SPECIFICATION
FAN5068
Block Diagrams
5V DUAL
+12
Q4
+5VSB
C13
5V MAIN
SBSW
BOOT
S3#O
+5VSB
VCC
C4
EN
S3#I
C3
R5
SS
ILIM
PGOOD
3.3 MAIN
VCC
Q5
3.3 ALW
VDDQ C12
Q6
1.2 OUT
C17
R7
G1.2
FB1.2
R8
S3
SYS
LDOs
VTT
LDO
LDRV
GND
FB
C9
COMP
VDDQ IN
REF IN
VTT SNS
VTT OUT
C8
C7
C10
R10
R6
R1
C6
C11
R9
PWM
ISNS
HDRV
SW
R3
Q2
R2
L1
VDDQ
C
OUT
Q1
C2
C1
C5
L2
R4
Q3
+5MAIN
Figure 1. DDR/ACPI System Regulation Schematic
The components selected are for a 15A ouput on VDDQ.
Table 1. BOM for Figure 1
Description
See notes below
See notes below
Capacitor 1uF, 10%, 16VDC, X7R, 1206
Capacitor 10nF, 10%, 100VDC, X7R, 0805
Capacitor 2.2nF, 10%, 50V, X7R, 0805
Capacitor 33pF, 10%, 50VDC, NPO, 0805
Capacitor 10nF, 10%, 100VDC, X7R, 0805
Capacitor 220nF, 20%, 10VDC, X5R, 0603
Capacitor 100nF, 10%, 25VDC, X7R, 0805
Inductor 1.8uH, 3.24m
Ω
, 16 Amps, 20%, 0.5"
Inductor 0.39uH, 2.8m
Ω
, 15 Amps, 20%, 0.25"
MOSFET N-CH, 8.8m
Ω
, 30V, 50A, D-PAK, FSID:
FDD6296
2
Qty
Ref.
COUT
C1, C12,
C17
Vendor
Part Number
2
1
1
1
2
1
1
1
1
1
C2, C4
C3
C6
C9
C10, C11
C5
C8
L1
L2
Q1
KEMET
Panasonic
AVX
Panasonic
Panasonic
AVX
Kemet
Inter-Technical
Inter-Technical
Fairchild
C1206C105K4RACTU
ECJ-2VB2A103K
08055C222KAT2A
ECJ-2VC1H330J
ECJ-2VB2A103K
06033D224MAT
C0805C104K3RACTU
SC5018-1R8M
SC7232-R39M
FDD6296
REV. 1.0.1 9/9/04
FAN5068
PRODUCT SPECIFICATION
Table 1. BOM for Figure 1
(continued)
Description
MOSFET N-CH, 6m
Ω
, 30V, 75A, D-PAK, FSID:
FDD6606
MOSFET N-CH, 32m
Ω
, 20V, 21A, D-PAK, FSID:
FDD6530A
MOSFET P-CH, 35m
Ω
, -20V, -5.5A, SSOT-6,
FSID: FDC602P
Resistor 1.82k
Ω
, 1%, 0805
Resistor 56k
Ω
, 1%, 0805
Resistor 60.4k
Ω
, 1%, 0805
Resistor 3.01k
Ω
, 1%, 0603
Resistor 9.09k
Ω
, 1%, 0603
Resistor 10k
Ω
, 1%, 0805
Resistor 1k
Ω
, 1%, 0805
IC System Regulator, MLP 24-Pin 5X5mm
Qty
1
3
1
4
1
1
1
1
1
1
1
Ref.
Q2
Q3, Q6,
Q5
Q4
R1, R2,
R9, R10
R5
R6
R7
R8
R4
R3
U2
Vendor
Fairchild
Fairchild
Fairchild
Yageo
Any
Any
Part Number
FDD6606
FDD6530A
FDC602P
9C08052A1821FKHFT
Any
Any
Fairchild
FAN5068
Bypass Capacitor Notes:
Input capacitor C1 is typically chosen based on the ripple
current requirements. COUT is typically selected based on
both current ripple rating and ESR requirement. See AN-
6006 for these calculations.
C17 and C12 selection will be largely determined by ESR
and load transient response requirements. In each case, the
number of capacitors required depends on the capacitor tech-
nology chosen. Oscons can meet the requirements with less
space, but higher cost than using low ESR electrolytics (like
Rubycon MBZ).
5V
D2
BOOT
C
BOOT
VIN
Q1
EN
S3
POR/UVLO
S3
HDRV
OVP
FB
RAMP
Q
S R
PWM
4.41K
SW
VDDQ
Q2
L
OUT
C
OUT
ADAPTIVE
GATE
CONTROL LOGIC
PWM
VDD
LDRV
PGND
VIN
OSC
CLK
COMP
FB
S/H
RAMP
ILIM det.
ISNS
ISNS
R
SENSE
CURRENT PROCESSING
SS
PGOOD
VDDQ IN
Reference and
Soft Start
VREF
ILIM
R
ILIM
Figure 2. PWM Modulator Block Diagram
REV. 1.0.1 9/9/04
3
PRODUCT SPECIFICATION
FAN5068
VDDQ IN
S3
R9
REF IN
50K
VDDQ IN
R10
EN
+
50K
VTT OUT
–
VTT SNS
PGND
Figure 3. VTT Regulator Block Diagram
Pin Configuration
REF IN
COMP
GND
19
18
17
16
24
23
22
21
20
G1.2
FB1.2
SBSW
5V MAIN
VTT SNS
VTT OUT
ILIM
SS
FB
1
2
3
EN
S3#I
S3#O
3.3 ALW
VCC
PGOOD
P1 = GND
4
5
6
7
8
9
10
11
12
15
14
13
HDRV
SW
BOOT
ISNS
FAN5068MP 5x5 mm MLP-24 Package (
θ
JA
= 38°C/W,
θ
JC
= 1.4°C/W)*
Note: Connect P1 pad to GND.
Pin Definitions
Pin #
1
2
3
4
5
6
7
Pin Name
G1.2
FB1.2
SBSW
5V MAIN
VTT SNS
VTT OUT
VDDQ IN
Pin Function Description
Gate Drive for the 1.2V LDO
. Turned off (low) in S3 and S5 modes.
Feedback for the 1.2V LDO Output
. Tie to a voltage higher than 0.9V to disable this
regulator.
Standby Switch
. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in
S3. Goes high in S0 and S5.
5V MAIN
. When this pin is below 4.5V, transition from S3 to S0 is inhibited.
VTT Remote Sense Input
.
VTT Regulator Power Output
.
VDDQ Input from PWM
. Connect to PWM output voltage. This is the VTT Regulator power
input.
*Test method as per JEDEC Specification JESD51-5
4
VDDQ IN
LDRV
REV. 1.0.1 9/9/04
FAN5068
PRODUCT SPECIFICATION
Pin Definitions
(continued)
Pin #
8
9
10
11
12
13
Pin Name
BOOT
HDRV
SW
ISNS
LDRV
PGOOD
Pin Function Description
Boot
. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC
contains a boot diode to VCC.
High-Side Drive
. High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
Switching Node
. Return for the high-side MOSFET driver and a current sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
Current Sense Input
. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
Low-Side Drive
. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
Power Good Flag
. An open-drain output that will pull LOW when FB is outside of a ±10%
range of the 0.9V reference and the LDO outputs are > 80% or < 110% of its reference.
PGOOD goes low when S3 is high. The power good signal from the PWM regulator enables
the VTT regulator and the LDO controller.
VCC
. The IC takes its bias power from this pin. Also used for gate drive power. The IC is held
in standby until this pin is above 4.35V (UVLO threshold).
3.3V LDO Output
. Internal LDO output. Turned off in S0, on in S5 or S3 modes.
S3# Output
. Open-drain output which pulls the gates of two N-Channel blocking MOSFETs
low in S5 and S3. This pin goes high (open) in S0 mode.
S3 Input
. When LOW, turns off the VTT and 1.2V LDO regulators and turns on the 3.3V
regulator. Also causes S3#O to pull low to turn off blocking switch Q3 as shown in Figure 1.
PGOOD is low when S3#I is LOW.
ENABLE
. Typically tied to S5#. When this pin is low, the IC is in a low quiescent current
state, all regulators are off and S3#O is low.
GROUND
for the IC are tied to this pin and also connected to P1.
Current Limit
. A resistor from this pin to GND sets the current limit.
Soft Start
. A capacitor from this pin to GND programs the slew rate of the converter during
initialization as well as sets the initial slew rate of the LDO controllers when transitioning from
S3 to S0. This pin is charged/discharged with a 5µA current source during initialization, and
charged with 50µA during PWM soft-start.
Output of the PWM error amplifier
. Connect compensation network between this pin and
FB.
VDDQ Feedback
. The feedback from PWM output. Used for regulation as well as PGOOD,
under-voltage, and over-voltage protection and monitoring.
VTT Reference
. Input which provides the reference for the VTT regulator. A precision
internal divider from VDDQ IN is provided.
14
15
16
17
VCC
3.3 ALW
S3#O
S3#I
18
19
20
21
EN
GND
ILIM
SS
22
23
24
COMP
FB
REF IN
REV. 1.0.1 9/9/04
5
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