NJU3712
8-BIT SERIAL TO PARALLEL CONVERTER
GENERAL DESCRIPTION
The
NJU3712
is an 8-bit serial to parallel converter
especially applying to MPU outport expander. It can
operate from 4.5V to 5.5V.
The effective outport assignment of MPU is available
as the connection between
NJU3712
and MPU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
Furthermore, the
NJU3712
outputs the serial data
from SO terminal through the shift register. Therefore, it
connects with other SIPO ICs like as NJU3711 in
cascade for expanding the parallel conversion outputs.
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
PACKAGE OUTLINE
NJU3712D
NJU3712M
FEATURES
8-Bit Serial In Parallel Out
Cascade Connection
Hysteresis Input
0.5V typ
Operating Voltage
4.5 to 5.5V
Maximum Operating Frequency 5MHz
Output Current
25mA
C-MOS Technology
Package Outline
DIP16 / DMP16
PIN CONFIGURATION
P3
P4
P5
V
SS
P6
P7
P8
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
P2
P1
V
SS
CLR
STB
CLK
DATA
NJU3712D/M
BLOCK DIAGRAM
DATA
Shift Register
Latch Circuit
CLK
P1
P2
P3
P7
P8
SO
STB
CLR
Controller Circuit
Ver.2017-12-07
-1-
NJU3712
TERMINAL DESCRIPTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
P3
P4
P5
V
SS
P6
P7
P8
SO
DATA
CLK
STB
CLR
V
SS
P1
P2
V
DD
I/O
O
O
O
-
O
O
O
O
I
I
I
I
-
O
O
-
FUNCTION
Parallel Conversion Data Output Terminals
GND
Parallel Conversion Data Output Terminals
Serial Data Output Terminal
Serial Data Input Terminal
Clock Signal Input Terminal
Strobe Signal Input Terminal
Clear Signal Input Terminal
GND
Parallel Conversion Data Output Terminals
Power Supply Terminal (4.5 to 5.5V)
-2-
Ver.2017-12-07
NJU3712
NJU3555
FUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
the clock signal should be controlled for data order.
(3) Cascade Connection
The serial data input from DATA terminal is output from the SO terminal through internal shift register
unrelated with the CLR and STB status.
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
to protect the noise.
CLK
X
STB
X
H
L
H
L
H
CLR
L
H
OPERATION
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
Note 1)
X: Don’t care
Ver.2017-12-07
-3-
NJU3712
TIMING CHART
CLK
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
SO
-4-
Ver.2017-12-07
NJU3712
NJU3555
ABSOLUTE MAXIMUM RATINGS
(Ta=25C)
PARAMETER
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Output Current
Output Short Current
(SO Terminal)
(Note 5)
SYMBOL
V
DD
V
I
V
O
I
O
I
OS
RATINGS
-0.5
~
+7.0
V
SS
-0.5
~
V
DD
+0.5
V
SS
-0.5
~
V
DD
+0.5
±25
V
O
=7V, V
I
=0V
V
O
=0V, V
I
=7V
V
O
=7V, V
I
=0V
V
O
=0V, V
I
=7V
10 (max)
-10 (max)
20 (max)
-20 (max)
UNIT
V
V
V
mA
mA
Output Short Current
(P1~P8 Terminals)
(Note 5)
I
OSD
P
D
Topr
Tstg
mA
mW
C
C
Power Dissipation
Operating Temperature Range
Storage Temperature Range
700 (DIP)
300 (DMP)
-25
~
+85
-65
~+150
Note 2)
All voltage are relative to V
SS
=0V reference.
Note 3)
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also
Note 4)
Note 5)
recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause
malfunctions and impact on the reliability.
To stabilize the IC operation, place decoupling capacitor between V
DD
and V
SS
.
V
DD
=7V, V
SS
=0V, less than 1 second per pin.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Operating Current
High-level Output Voltage
Low-level Output Voltage
High-level Input Voltage
Low-level Input Voltage
Input Leakage Current
High-level Output Voltage
(Note 6)
SYMBOL
(V
DD
=4.5~5.5V, V
SS
=0V, Ta=25C, unless otherwise noted)
CONDITION
MIN
TYP
MAX
UNIT
4.5
V
IH
=V
DD
, V
IL
=V
SS
I
OH
=-0.4mA
I
OL
=+3.2mA
SO
Terminal
V
DD
I
DDS
V
OH
V
OL
V
IH
V
IL
I
LI
V
I
=0
~
V
DD
I
OH
=-25mA
P1~P8
Terminals
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
0.1
V
mA
V
V
V
V
µA
-
4.0
V
SS
0.7V
DD
V
SS
-10
V
DD
-1.5
V
DD
-1.0
V
DD
-0.5
V
SS
P1~P8
Terminals
V
DD
0.4
V
DD
0.3V
DD
10
V
DD
V
DD
V
DD
1.5
0.8
0.4
V
OHD
V
DD
=5V
I
OH
=-15mA
I
OH
=-10mA
I
OL
=+25mA
V
Low-level Output Voltage
(Note 6)
V
OLD
V
DD
=5V
I
OL
=+15mA
I
OL
=+10mA
V
SS
V
SS
V
Note 6)
Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating
operation should be required.
Ver.2017-12-07
-5-
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