MIC74
2-Wire Serial I/O Expander and Fan
Controller
General Description
The MIC74 is a fully programmable serial-to-parallel I/O
expander compatible with the SMBus™ (system manage-
ment bus) protocol. It acts as a slave on the bus, providing
eight independent I/O lines.
Each I/O bit can be individually programmed as an input or
output. If programmed as an output; each I/O bit can be
programmed as an open-drain or complementary push-pull
output. If desired, the four most significant I/O bits can be
programmed to implement fan speed control. An internal
clock generator and state machine eliminate the overhead
generally associated with “bit-banging” fan speed control.
Programming the device and reading/writing the I/O bits is
accomplished using seven internal registers. All registers
can be read by the host. Output bits are capable of directly
driving high-current loads, such as LEDs. A separate
interrupt output can notify the host of state changes on the
input bits without requiring the MIC74 to perform a
transaction on the serial bus or be polled by the host.
Three address selection inputs are provided, allowing up
to eight devices to share the same bus and provide a total
of 64 bits of I/O.
The MIC74 is available in an ultra-small-footprint 16-pin
QSOP. Low quiescent current, small footprint, and low
package height make the MIC74 ideal for portable and
desktop applications.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
Provides eight bits of general purpose I/O
•
Built-in fan speed control logic (optional)
2
•
2-wire SMBus™/I C™-compatible serial interface plus
interrupt output
•
2.7V to 3.6V operating voltage range
•
5V-tolerant I/O
•
Low quiescent current: 2µA (typical)
•
Bit-programmable I/O options:
−
Input or output
−
Push-pull or open-drain output
−
Interrupt on input changes
•
Outputs can directly drive LEDs (10mA I
OL
)
•
Up to 8 devices per bus
Applications
•
•
•
•
•
General purpose I/O expansion via serial bus
Personal computer system management
Distributed sensing and control
Microcontroller I/O expansion
Fan control
Typical Application
SMBus is a trademark of Intel Corporation. I
2
C is a trademark of Phillips Electronics N.V.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
September 30, 2014
Revision 3.0
Micrel, Inc.
MIC74
Ordering Information
Part Number
MIC74YQS
Junction Temperature Range
–40°C to +85°C
Package
16-Pin QSOP
Lead Finish
Pb-Free
Pin Configuration
16-Pin QSOP (QS)
(Top View)
Pin Description
Pin Number
1, 2, 3
4, 5, 6, 7
8
Pin Name
A0, A1, A2
P0, P1,
P2, P3
GND
P4, P5,
P6, P7
(/SHDN, /FS0
/FS1, /FS2)
Pin Function
Address (input): Slave address selection inputs; sets the three least significant bits of the MIC74’s
slave address.
Parallel I/O (input/output): General-purpose I/O pin. Direction and output type are user-
programmable.
Ground
Parallel I/O (input/output): P4–P7 are general-purpose I/O pins. Direction and output type are
user-programmable.
Shutdown (output): When the FAN bit is set, pin 9 becomes SHDN.
Fan speed (output): When the FAN bit is set, pins 10 through 12 become /FS0 – /FS2
respectively, controlled by the FAN_SPEED register.
Interrupt (output): Active-low, open-drain output signals input-change-interrupts to the host on this
pin. Signal is cleared when the bus master (host) polls the ARA (alert response address = 0001
100) or reads status.
Serial bus clock (input): The host provides the serial bit clock in this input.
Serial data (input/output): Serial data input and open-drain serial data output.
Power supply (input).
9, 10, 11, 12
13
14
15
16
/ALERT
CLK
DATA
VDD
September 30, 2014
2
Revision 3.0
Micrel, Inc.
MIC74
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
) ................................................... +4.6V
Input Voltage [all pins except VDD
and GND] (V
IN
). .................................. GND – 0.3V to +5.5V
Junction Temperature (T
J
) ......................................... 150°C
Lead Temperature (soldering, 10s) ............................ 260°C
(3)
ESD Rating
VDD ...................................................................... 1.5kV
A0, A1, A2 .............................................................. 500V
Others .................................................................... 200V
Operating Ratings
(2)
Supply Voltage (V
DD
) .................................... +2.7V to +3.6V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
Package Thermal Resistance (θ
JA
) ........................ 163°C/W
Electrical Characteristics
(4)
2.7V ≤ V
DD
≤ 3.6V; T
A
= 25°C, bold values indicate –40°C < T
A
< +85°C, unless noted.
Symbol
V
IN
I
DD
Parameter
Input Voltage (any pin except
VDD and GND)
Operating Supply Current
P[7:0] inputs; P[7:0] = V
DD
or GND
/ALERT open; f
CLK
= 100kHz
during t
START
; /ALERT, /SHDN,
/FS2[2:0] = open;
V
CLK
= V
DATA
= V
DD
;
P[3:0] = inputs
/ALERT = open,
V
CLK
= V
DATA
= V
DD
;
P[3:0] = inputs
1
Condition
Min.
GND–0.3
2
Typ.
Max.
5.5
6
Units
V
µA
I
START
Fan Startup Supply Current
(Fan Mode Only)
1.75
mA
I
STBY
Standby Supply Current
3
µA
Serial I/O (DATA, CLK)
V
IL
V
IH
V
OL
I
LEAK
C
IN
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. Devices participating in a transfer will timeout when any clock low exceeds the value of t
TIMEOUT(min)
of 25ms. Devices that have detected a timeout
condition must reset the communication no later than t
TIMEOUT(max)
of 35ms. The maximum value specified must be adhered to by both a master and a
slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
6. t
HIGH(max)
provides a simple guaranteed method for devices to detect bus idle conditions.
7. Rise and fall time is defined as follows: t
R
= V
IL(max)
– 0.15V to V
IH(min)
+ 0.15V; t
F
= 0.9V
DD
to V
IL(max)
– 0.15V.
8. Guaranteed by design.
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
Input Capacitance
I
OL
= 3mA
V
IN
= 5.5V or GND
–0.3
2
0.8
5.5
0.4
V
V
V
µA
pF
–1
10
+1
September 30, 2014
3
Revision 3.0
Micrel, Inc.
MIC74
Electrical Characteristics
(4)
(Continued)
Parallel I/O [P0–P3, P4(/SHDN), P5(/FS0)–P7(/FS2)]
Symbol
V
IL
V
IH
I
OL
I
OH
I
LEAK
C
IN
C
OUT
Parameter
Input Low Voltage
Input High Voltage
Output Low Current
Output High Current
Leakage Current
Input Capacitance
Output Capacitance
V
OL
= 0.4V, V
DD
= 2.7V
V
OL
= 1V, V
DD
= 3.3V
V
OH
= 2.4V
V
IN
= 5.5V or GND
Condition
Min.
–0.5
2
7
10
7
–1
10
10
+1
Typ.
Max.
0.8
5.5
Units
V
V
mA
mA
mA
µA
pF
pF
Address Input (A0–A2)
V
IL
V
IH
I
LEAK
/ALERT
V
OL
I
LEAK
Output Low Voltage
Leakage Current
I
OL
= 1mA
V
IN
= V
DD
or V
SS
–1
±250
0.4
+1
V
µA
Input Low Voltage
Input High Voltage
Leakage Current
V
IN
= V
DD
or GND
–0.3
0.7V
DD
–250
0.3V
DD
V
DD
+0.3
+250
V
V
nA
AC Characteristics
t
START
t
PULSE
t
/INT
t
/IR
Fan Startup Interval
Minimum Pulse-Width
Interrupt Delay
Delay from Status Read or ARA
Response to /ALERT ≥ V
OH
Hold Time,
Note 8
Setup Time,
Note 8
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Time-Out
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Bus free time between stop and
Start condition
Hold time after repeated start condition,
after this period, the first clock is
generated
Repeated start condition setup time
Note 8
Note 8
Note 8
Note 5, 8
Note 6, 8
Note 6, 8
Note 7, 8
Note 7, 8
Note 8
4.7
4
4.7
4
500
0
25
4.7
4
50
300
1000
35
Normal operation
Minimum pulse-width on Pn to generate
an interrupt,
Note 8
Interrupt delay from state change on Pn to
/ALERT ≤ V
OL
,
Note 8
0.5
10
4
4
1
3.3
sec
ns
µs
µs
t
HD:STA
t
SU:STA
t
SU:STO
t
HD:DAT
t
SU:DAT
t
TIMEOUT
t
LOW
t
HIGH
t
F
t
R
t
BUF
µs
µs
µs
ns
ns
ms
µs
µs
ns
ns
µs
September 30, 2014
4
Revision 3.0
Micrel, Inc.
MIC74
Timing Definitions
Register Descriptions
Table 1. Device Configuration Register
DEV_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
FAN
D[0]
IE
Always write as zero
Device Configuration Register Parameters
•
Power-on default value: 0000 0000
b
, 00
h
−
−
•
•
•
•
Interrupts disabled
Not in fan mode
•
•
•
•
•
•
•
Operation: 1 = enabled; 0 = disabled
Bit name: FAN
Function: Selects fan mode (P[7:4] vs. /FS[2:0],
/SHDN)
Operation: 1 = fan mode; 0 = I/O mode
Bit Name: D[2] through D[6]
Function: Reserved
Operation: Reserved; always write as zero
Command_byte address: 0000 0000
b
, 00
h
Type: 8-bits, read/write
Bit name: IE
Function: Global interrupt enable
Table 2. Data Direction Register
DIR
D[7]
DIR7
D[6]
DIR6
D[5]
DIR5
D[4]
DIR4
D[3]
DIR3
D[2]
DIR2
D[1]
DIR1
D[0]
DIR0
Data Direction Register Parameters
•
•
•
•
•
•
•
Power-on default value: 0000 0000
b
, 00
h
−
All Pn’s configured as inputs
Command_byte address: 0000 0001
b
, 01
h
Type: 8-bits, read/write
Bit name: DIRn
Function: Selects data direction, input or output, of Pn
Operation: 1 = output; 0 = input
•
Notes: If the FAN bit of the DEV_CFG register is set to
‘1’ (i.e., if fan mode is selected), P[7:4] are
automatically configured as open-drain outputs. They
are then referred to as /FS[2:0] and /SHDN. The DIR
register has no effect on these I/O bits while in fan
mode.
September 30, 2014
5
Revision 3.0
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