74HC4515
Rev. 3 — 2 July 2018
4-to-16 line decoder/demultiplexer with input latches;
inverting
Product data sheet
1
General description
The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted
address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and
16 inverting outputs (Q0, to Q15).
When LE is HIGH, the selected output is determined by the data on An. When LE goes
LOW, the last data present at An are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the contents of the latch, is LOW.
When E is HIGH, all outputs are HIGH. The enable input E does not affect the state of
the latch. When the device is used as a demultiplexer, E is the data input and A0 to A3
are the address inputs.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
2
Features and benefits
•
•
•
•
•
•
Inverting outputs
CMOS input levels
16-line demultiplexing capability
Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
Complies with JEDEC standard no. 7 A
ESD protection:
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3
Applications
•
Digital multiplexing
•
Address decoding
•
Hexadecimal/BCD decoding
4
Ordering information
Package
Temperature range
Name
SO24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
Version
SOT137-1
−40 °C to +125 °C
Table 1. Ordering information
Type number
74HC4515D
Nexperia
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC4515
5
Functional diagram
Q0
Q1
1
2
3
21
22
23
LE
A0
A1
A2
A3
E
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
23
2
3
21
22
3
0
4D, G
0
15
1
C4
DX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
23
EN
2
3
21
22
9D, 1
9D, 2
9D, 4
9D, 8
1
C9
X/Y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
aaa-028693
aaa-028694
Figure 1. Logic symbol
2
A0
1
LE
3
Figure 2. IEC logic symbol
21
A1
A2
22
A3
LATCHES
23
E
DECODER
Q0
11
9
Q1
Q2
10
8
Q3
7
Q4
6
Q5
5
Q6
4
Q7
Q8
18
Q9
17
Q10 Q11 Q12 Q13 Q14 Q15
20
19
14
13
16
aaa-028695
15
Figure 3. Functional diagram
74HC4515
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 2 July 2018
2 / 14
Nexperia
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC4515
Q0
A0
SD
latch
1
RD
Q
Q
Q1
Q2
Q3
A1
SD
latch
2
RD
Q4
Q
Q
Q5
Q6
Q7
A2
SD
latch
3
RD
Q8
Q
Q
Q9
Q10
Q11
A3
SD
latch
4
RD
Q12
Q
Q
Q13
Q14
Q15
aaa-028696
LE
E
Figure 4. Logic diagram
74HC4515
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 2 July 2018
3 / 14
Nexperia
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC4515
6
Pinning information
6.1 Pinning
74HC4515
LE
A0
A1
Q7
Q6
Q5
Q4
Q3
Q1
1
2
3
4
5
6
7
8
9
24 V
CC
23 E
22 A3
21 A2
20 Q10
19 Q11
18 Q8
17 Q9
16 Q14
15 Q15
14 Q12
13 Q13
aaa-028697
Q2 10
Q0 11
GND 12
Figure 5. Pin configuration for SO24 (SOT137-1)
6.2 Pin description
Table 2. Pin description
Symbol
LE
E
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15
A0, A1, A2, A3
GND
V
CC
Pin
1
23
11, 9, 10, 8, 7, 6, 5, 4,
18, 17, 20, 19, 14, 13, 16, 15
2, 3, 21, 22
12
24
Description
latch enable input (active HIGH)
enable input (active LOW)
multiplexer outputs (active LOW)
address inputs
ground (0 V)
supply voltage
74HC4515
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 2 July 2018
4 / 14
Nexperia
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC4515
7
Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Inputs
E
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[1]
Outputs
A1
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Q0
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q1
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q2
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
Q3
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
Q4
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
Q5
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Q6
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
Q7
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
Q8
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
Q9
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
Q10 Q11 Q12 Q13 Q14 Q15
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
A0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
[1] LE = HIGH
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO24
[1]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
Min
-0.5
-
-
-
-
-50
-65
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
[1] P
tot
derates linearly with 8 mW/K above 70 °C.
74HC4515
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 2 July 2018
5 / 14
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
