TBD62089APG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TBD62089APG
8-ch Sink Type DMOS Transistor Array with D-type Flip-Flop
The TBD62089APG is an 8-ch DMOS transistor array with
D-type flip-flop. Please be careful about thermal conditions during use.
Features
•
•
•
•
Built-in 8 circuits
High output voltage
High output current
Package
: V
OUT
= 50 V (max)
: I
OUT
= 500 mA/ch (max)
: DIP20-P-300-2.54A
DIP20-P-300-2.54A
Weight: 1.4 g (typ.)
Pin assignment (top view)
VDD
/Y1
/Y2
/Y3
/Y4
/Y5
/Y6
/Y7
/Y8
GND
/CLR
D1
D2
D3
D4
D5
D6
D7
D8
CLK
©2016 Toshiba Corporation
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TBD62089APG
Pin description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin name
/CLR
D1
D2
D3
D4
D5
D6
D7
D8
CLK
GND
/Y8
/Y7
/Y6
/Y5
/Y4
/Y3
/Y2
/Y1
VDD
Function
Clear signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Data signal input pin
Clock signal input pin
Ground pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Power supply pin
Block diagram
/Y1
/Y2
/Y3
/Y4
/Y5
/Y6
/Y7
/Y8
VDD
CLK
/CLR
D
100kΩ
(typ.)
100kΩ
(typ.)
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
D1
D2
D3
D4
D5
Equivalent circuit may be omitted or simplified for explanatory purpose.
D6
D7
D8
GND
Function table
OUTPUT: /Y
/CLR
D
L
X
H
H
L
H
H
H
L
H
X
Y0
H
X
Y0
↑:
”L”
to
”H”
↓:
”H”
to
”L”
H: High level
L: Low level
X: Don’t care
Y0: /Y level just before inputting conditions in the table are fixed
*: Operating conditions in the table: OUTPUT is connected to the power supply through resistors.
INPUT
CLK
X
↑
↑
L
↓
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TBD62089APG
Absolute maximum ratings (T
a
= 25°C)
Characteristics
Output voltage
Power supply voltage
Output current
Input voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
V
OUT
V
DD
I
OUT
V
IN
P
D
(Note1)
T
opr
T
stg
Rating
50
−0.5 to 6
500
−0.5 to 6
1.76 (Note2)
−40 to 85
−55 to 150
Unit
V
V
mA/ch
V
W
°C
°C
Note1: In mounting on a board, based on JEDEC 2s2p standards
Note2: When Ta exceeds 25 °C, derating with 14.1 mW/°C is necessary.
Operating range (T
a
= - 40 to 85°C, unless otherwise specified)
Characteristics
Output voltage
Power supply voltage
Output current (per channel)
(Note)
Symbol
V
OUT
V
DD
t
pw
= 25 ms
8 channels ON
T
a
= 85°C
T
j
= 120°C
―
―
V
DD
= 3 V to 5.5 V
V
DD
= 3 V to 5.5 V
V
DD
= 3 V to 5.5 V
Setup time of D input for CLK input
V
DD
= 3 V to 5.5 V
Hold time of D input for CLK input
V
DD
= 3 V to 5.5 V
V
DD
= 3 V to 5.5 V
Test conditions
―
―
1 channel ON, T
a
= 25 °C
I
OUT
Duty = 10 %
Duty = 50 %
Min
―
3
0
0
0
0.7×V
DD
0
0
0
10
10
30
―
Typ.
―
―
―
―
―
―
―
―
―
―
―
―
―
Max
50
5.5
400
400
195
V
DD
0.3×V
DD
500
500
―
―
―
20
V
V
ns
ns
ns
ns
ns
MHz
mA
Unit
V
V
Input voltage (Output on)
Input voltage (Output off)
Voltage rising time of CLK input
Voltage falling time of CLK input
Setup time
Hold time
Pulse width (CLK, /CLR)
Logic clock frequency
V
IN (ON)
V
IN (OFF)
t
r
t
f
t
su
t
h
t
w
f
CLK
Note: In mounting on a board, based on JEDEC 2s2p standards
Timing chart
CLK
50%
t
w
D
50%
t
su
t
h
50%
50% 10% 90% 90%
t
r
t
f
10%
Timing charts may be omitted or simplified for explanatory purposes.
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TBD62089APG
Electrical characteristics (T
a
= 25°C and V
DD
= 5 V, unless otherwise specified)
Characteristics
Output leakage current
Symbol
I
leak
Test
Circuit
1
Test conditions
V
OUT
= 50 V, T
a
= 85 °C
V
IN
= 0 V
I
OUT
= 350 mA
Output voltage
(Output ON-resistance)
V
DS
(R
ON
)
2
I
OUT
= 200 mA
I
OUT
= 100 mA
Input current (Output on)
Input current (Output off)
Power supply current
(per channel)
I
IN (ON)
I
IN (OFF)
I
CC (ON)
I
CC (OFF)
t
p
HL (CLK)
3
4
3
4
5
V
IN
= 5.5 V, V
DD
= 5.5 V
V
IN
= 0 V, V
DD
= 5.5 V
V
IN
= 5.5 V, V
DD
= 5.5 V
V
IN
= 0 V, V
DD
= 5.5 V
CLK (50 %) to /Y (50 %)
/Y: H to L
C
L
= 30 pF
R
L
= 240
Ω,
pull-up to 24 V
CLK (50 %) to /Y (50 %)
/Y: L to H
C
L
= 30 pF
R
L
= 240
Ω,
pull-up to 24 V
/CLR (50 %) to /Y (50 %)
/Y: L to H
C
L
= 30 pF
R
L
= 240
Ω,
pull-up to 24 V
/Y waveform: 10 % to 90 %
C
L
= 30 pF
R
L
= 240
Ω,
pull-up to 24 V
/Y waveform: 90 % to 10 %
C
L
= 30 pF
R
L
= 240
Ω,
pull-up to 24 V
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 3.6 V
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 3.6 V
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 3.6 V
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 3.6 V
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 3.6 V
Min
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Typ.
―
0.56
(1.6)
0.32
(1.6)
0.16
(1.6)
―
―
―
―
270
470
350
350
350
350
280
280
330
620
Max
1.0
1.14
(3.25)
0.65
(3.25)
0.325
(3.25)
80
1.0
75
1.0
430
ns
670
510
ns
510
510
ns
510
400
400
480
860
ns
ns
μA
μA
μA
μA
V
(Ω)
Unit
μA
Propagation delay time
t
p
LH (CLK)
5
t
p
LH
(/CLR)
5
Turn-on delay time
t
or
5
Turn-off delay time
t
of
5
Timing chart
CLK
50%
50%
/Y
t
pHL(CLK)
/CLR
50%
50%
t
pLH(CLK)
90%
t
of
10%
10%
t
or
90%
50%
/Y
t
pLH(/CLR)
50%
Timing charts may be omitted or simplified for explanatory purposes.
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TBD62089APG
Test circuit
1. I
leak
PG
(/Y = H)
D
CLK
/CLR
VDD
/Y
GND
2. V
DS
(R
ON
)
PG
(/Y = L)
D
CLK
/CLR
VDD
/Y
GND
I
leak
V
OUT
V
DD
I
OUT
V
DS
V
DD
R
ON
= V
DS
/ I
OUT
3. I
IN (ON)
and I
CC (ON)
4. I
IN (OFF)
and I
CC (OFF)
I
IN(ON)
I
IN(ON)
I
IN(ON)
V
IN
V
IN
D
CLK
/CLR
VDD
/Y
GND
I
IN(OFF)
I
IN(OFF)
I
IN(OFF)
V
DD
V
IN
V
IN
D
CLK
/CLR
VDD
/Y
GND
V
DD
V
IN
V
IN
5. t
pHL (CLK)
, t
pLH (CLK)
, t
pLH (/CLR)
, t
or
, and t
of
D
CLK
/CLR
VDD
/Y
GND
PG
C
L
R
L
V
OUT
V
DD
Test circuits may be omitted or simplified for explanatory purposes.
5
2016-12-21
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