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74LV4094DB,118: 产品描述IC 8BIT SHIFT/STORE BUS 16SSOP; 产品类别逻辑逻辑; 文件大小786KB，共20页; 制造商Nexperia; 官网地址https://www.nexperia.com; 标准

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74LV4094DB,118概述

IC 8BIT SHIFT/STORE BUS 16SSOP

74LV4094DB,118规格参数

参数名称	属性值
Brand Name	Nexperia
是否Rohs认证	符合
厂商名称	Nexperia
零件包装代码	SSOP1
包装说明	5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16
针数	16
制造商包装代码	SOT338-1
Reach Compliance Code	compliant
Samacsys Description	74LV4094 - 8-stage shift-and-store bus register@en-us
其他特性	SISO OPERATION ALSO AVAILABLE
计数方向	RIGHT
系列	LV/LV-A/LVX/H
JESD-30 代码	R-PDSO-G16
JESD-609代码	e4
长度	6.2 mm
负载电容（CL）	50 pF
逻辑集成电路类型	SERIAL IN PARALLEL OUT
湿度敏感等级	1
位数	8
功能数量	1
端子数量	16
最高工作温度	125 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260
传播延迟（tpd）	90 ns
认证状态	Not Qualified
座面最大高度	2 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
触发器类型	POSITIVE EDGE
宽度	5.3 mm
最小 fmax	20 MHz
Base Number Matches	1

74LV4094DB,118文档预览

74LV4094

8-stage shift-and-store bus register

Rev. 5 — 18 March 2016

Product data sheet

1. General description

The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible

with 74HC4094; 74HCT4094.

The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with

each stage for strobing data from the serial input to parallel buffered 3-state outputs

QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is

shifted on positive-going clock transitions. The data in each shift register stage is

transferred to the storage register when the strobe (STR) input is HIGH. Data in the

storage register appears at the outputs whenever the output enable (OE) signal is HIGH.

Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094

devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed

operation in cascaded systems with a fast clock rise time. The same serial data is

available at QS2 on the next negative going clock edge. This is used for cascading

74LV4094 devices when the clock has a slow rise time.

2. Features and benefits



Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

C



ESD protection:



HBM JESD22-A114E exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Applications



Serial-to-parallel data conversion



Remote control holding register

Nexperia

74LV4094

8-stage shift-and-store bus register

4. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LV4094D

74LV4094DB

74LV4094PW

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

Name

SO16

SSOP16

TSSOP16

Description

Version

plastic small outline package; 16 leads; body width 3.9 SOT109-1

plastic shrink small outline package; 16 leads;

body width 5.3 mm

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT338-1

SOT403-1

Type number

5. Functional diagram

Fig 1.

Functional diagram

Fig 2.

Logic symbol

Fig 3.

Logic diagram

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 18 March 2016

2 of 20

Nexperia

74LV4094

8-stage shift-and-store bus register

Fig 4.

Logic diagram

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 18 March 2016

3 of 20

Nexperia

74LV4094

8-stage shift-and-store bus register

6. Pinning information

6.1 Pinning

Fig 5.

Pin configuration SO16, SSOP16 and TSSOP16

6.2 Pin description

Table 2.

Symbol

STR

QP0 to QP7

GND

QS1, QS2

Pin description

4, 5, 6, 7, 14, 13, 12, 11

9,10

Description

strobe input

data input

clock input

parallel output

ground supply voltage

serial output

output enable input

supply voltage

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 18 March 2016

4 of 20

Nexperia

74LV4094

8-stage shift-and-store bus register

7. Functional description

Table 3.

Inputs









[1]

Function table

[1]

Parallel outputs

STR

QP0

QPn

1

QPn

1

Serial outputs

QS1

Q6S

QS2

Q7S

At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;



= positive-going transition;



= negative-going transition;

Z = HIGH-impedance OFF-state; NC = no change;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

Fig 6.

Timing diagram

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 18 March 2016

5 of 20

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74LV4094DB,118相似产品对比

	74LV4094DB,118	74LV4094DB,112
描述	IC 8BIT SHIFT/STORE BUS 16SSOP	IC 8ST SHIFT/STORE BUS 16-SSOP
Brand Name	Nexperia	Nexperia
是否Rohs认证	符合	符合
厂商名称	Nexperia	Nexperia
零件包装代码	SSOP1	SSOP1
包装说明	5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16	5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16
针数	16	16
制造商包装代码	SOT338-1	SOT338-1
Reach Compliance Code	compliant	compliant
Samacsys Description	74LV4094 - 8-stage shift-and-store bus register@en-us	74LV4094 - 8-stage shift-and-store bus register@en-us
其他特性	SISO OPERATION ALSO AVAILABLE	SISO OPERATION ALSO AVAILABLE
计数方向	RIGHT	RIGHT
系列	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 代码	R-PDSO-G16	R-PDSO-G16
JESD-609代码	e4	e4
长度	6.2 mm	6.2 mm
负载电容（CL）	50 pF	50 pF
逻辑集成电路类型	SERIAL IN PARALLEL OUT	SERIAL IN PARALLEL OUT
湿度敏感等级	1	1
位数	8	8
功能数量	1	1
端子数量	16	16
最高工作温度	125 °C	125 °C
最低工作温度	-40 °C	-40 °C
输出特性	3-STATE	3-STATE
输出极性	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260	260
传播延迟（tpd）	90 ns	90 ns
认证状态	Not Qualified	Not Qualified
座面最大高度	2 mm	2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V
最小供电电压 (Vsup)	1 V	1 V
标称供电电压 (Vsup)	3.3 V	3.3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm
端子位置	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30
触发器类型	POSITIVE EDGE	POSITIVE EDGE
宽度	5.3 mm	5.3 mm
最小 fmax	20 MHz	20 MHz
Base Number Matches	1	1

74LV4094DB,118

74LV4094DB,118概述

74LV4094DB,118规格参数

74LV4094DB,118文档预览

74LV4094DB,118相似产品对比

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