SN751508, SN751518
DC PLASMA DISPLAY DRIVERS
SLDS035 – JANUARY 1987 – REVISED NOVEMBER 1989
D
D
D
D
D
D
Each Device Drives 32 Lines
–120-V PNP Open-Collector Parallel
Outputs
High-Speed Serially Shifted Data Inputs
CMOS-Compatible Inputs
Strobe and Sustain Inputs Provided
Serial Data Output for Cascade Operation
SN751508 . . . FT PACKAGE
(TOP VIEW)
description
The SN751508 and SN751518 are monolithic
integrated circuits designed to drive the data lines
of a dc plasma panel display. The SN751518 pin
sequence is reversed from the SN751508 for
ease in printed-circuit-board layout.
Each device consists of two 16-bit shift registers,
32 latches, 32 OR gates, and 32 pnp open-
collector output AND gates. Typically, a 32-bit
data string is split into two 16-bit data strings
externally and then entered in parallel into the shift
registers on the high-to-low transition of the clock
signal. A high LATCH ENABLE transfers the data
from the shift registers to the inputs of 32 OR gates
through the latches. Data present in the latch
during the high-to-low transition of LATCH
ENABLE is stored. When STROBE is high, the
latch is masked and a high is placed on the data
input of the output AND gates. When STROBE is
low and SUSTAIN is high, data from the latches is
reflected at the outputs. When low, SUSTAIN
forces all outputs to their off state. Drivers can be
cascaded via the serial data outputs of the static
shift registers. These outputs are not affected by
LATCH ENABLE, STROBE, or SUSTAIN.
The SN751508 and the SN751518
characterized from 0°C to 70°C.
are
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
Q17
GND
NC
STROBE
NC
CLOCK
V
CC
SERIAL OUT2
SERIAL OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
GND
SUSTAIN
NC
LATCH ENABLE
NC
V
CC
DATA IN2
DATA IN1
SN751518 . . . FT PACKAGE
(TOP VIEW)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
GND
SUSTAIN
NC
LATCH ENABLE
NC
V
CC
DATA IN2
DATA IN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
Q17
GND
NC
STROBE
NC
CLOCK
V
CC
SERIAL OUT2
SERIAL OUT1
NC – No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1989, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN751508, SN751518
DC PLASMA DISPLAY DRIVERS
SLDS035 – JANUARY 1987 – REVISED NOVEMBER 1989
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
CLOCK
↓
No
↓
X
X
X
X
LATCH
ENABLE
X
X
L
H
X
X
STROBE
X
X
X
X
L
H
SUSTAIN
X
X
X
X
H
H
SHIFT REGISTERS
R1 THRU R32
Load and shift†
No change
As determined
above
As determined
above
As determined
above
LATCHES
LC1 THRU
LC32
Determined by
LATCH
ENABLE‡
Stored data
New data
Determined by
LATCH
ENABLE‡
Determined by
LATCH
ENABLE‡
OUTPUTS
SERIAL
S01
R31
S02
R32
Q1 THRU Q32
Determined by
y
SUSTAIN and STROBE
Determined by
y
SUSTAIN and STROBE
LC1 thru LC32
All on (high)
Load
Latch
Enable
Strobe
R31
R32
R31
R32
Sustain
X
X
X
L
R31
R32
All off
H = high level, L = low level, X = irrelevant,
↓
= high-to-low transition
† Each even-numbered shift register stage takes on the state of the next-lower even-numbered stage, and likewise each odd-numbered shift
register stage takes on the state of the next-lower odd-numbered stage; i.e., R32 takes on the state of R30, R30 takes on the state of R28, ...
R4 takes on the state of R2, R2 takes on the state of DATA IN2, R31 takes on the state of R29, R29 takes on the state of R27, ... R3 takes on
the state of R1, and R1 takes on the state on DATA IN1.
‡ New data enters the latches while LATCH ENABLE is high. This data is stored while LATCH ENABLE is low.
typical operating sequence
...
CLOCK
DATA IN
Shift
Register
Contents
LATCH ENABLE
Valid
Irrelevant
Invalid
Valid
Latch Contents
STROBE
Previously Stored Data
New Data Valid
SUSTAIN
Q Outputs
Off State
Valid
Off State
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN751508, SN751518
DC PLASMA DISPLAY DRIVERS
SLDS035 – JANUARY 1987 – REVISED NOVEMBER 1989
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF ALL Q OUTPUTS
VCC2
TYPICAL OF SERIAL OUTPUT
VCC
Input
Output
Output
GND
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 to 7 V
On-state Q output voltage range, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 120 V to V
CC
+ 0.4 V
Input voltage range, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 V to V
CC
+ 0.4 V
Serial output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 V to V
CC
+ 0.4 V
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . 1025 mW
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: 1. Voltages values are with respect to GND.
2. For operation above 25°C free-air temperature, derate linearly to 656 mW at 70°C at the rate of 8.2 mW/°C.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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