UM10868
PCAL6524 demonstration board OM13526
Rev. 1 — 23 September 2015
User manual
Document information
Info
Content
Keywords
Abstract
OM13320 Fm+ development kit, OM13260 Fm+ I2C bus development
board, OM13303 GPIO target board
Installation guide and User Manual for the OM13526 24-bit GPIO
Daughter Card that connects to OM13260 Fm+ I2C bus development
board. This daughter board makes it easy to test and design with the
PCAL6524, an ultra low-voltage translating 24-bit general purpose I/O
expander that provides remote I/O expansion for most microcontroller
families via the Fast-mode Plus (Fm+) I2C-bus interface. This daughter
board, along with the Fm+ Development board, provides an easy to use
evaluation platform.
NXP Semiconductors
UM10868
PCAL6524 demonstration board OM13526
Revision history
Rev
Date
1
20150923
Description
Initial version.
Contact information
For more information, please visit:
http://www.nxp.com
UM10868
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
User manual
Rev. 1 — 23 September 2015
2 of 19
NXP Semiconductors
UM10868
PCAL6524 demonstration board OM13526
1. Introduction
The PCAL6524 24-bit GPIO evaluation board allow bidirectional voltage-level translation
and GPIO expansion between 0.8 V to 3.6 V on SCL/SDA and 1.8 V, 2.5 V, 3.3 V, 5.5 V
on I/O Ports with active low reset input control and open-drain active low interrupt output
indicator (red LED) plus one hardware address input setting to select one of four different
slave address. A graphical interface allows the user to easily explore the different
functions of the I/O expander.
The IC communicates to the host via the industry standard I
2
C-bus/SMBus port. The
evaluation software runs under Microsoft Windows PC platform.
2. Features of the OM13526 24-bit GPIO daughter board
•
Direct connection to OM13260 Fm+ I
2
C-bus Development board
•
Easy to use GUI based software demonstrates the capabilities of the PCAL6524
•
Jumper configuration for most features of PCAL6524
•
Flexible power supply configuration: 3.3 V, 5 V or external supply
•
Direct connection to OM13303 GPIO Target board for I/O visualization
•
Convenient test points for easy scope measurements and signal access
•
Jumper configuration of device I
2
C address
•
LED indicators for power and /INT
•
No external power supply required and obtains +5 V power from PC USB port
3. Hardware description
3.1 Power supply jumpers
The power supply selection for the OM13526 is very flexible and allows for detailed
analysis and evaluation of 24-bit GPIO device. J13 selects +5V_PWR supply from either
the tester connector CN1 (pins 4 and 6, +5V_TSTR) or the Fm+ board connector CN2
(pins 7 and 12, +5V). J1 selects VDDP (U1 pin 27) supply from either +5V_PWR or +3V3
(CN2 pins 8 and 11) and J9 selects VDDI (U1 pin 31) supply from either +3V3 (CN2 pins
8 and 11) or +5V_PWR. If external power operation is desired from TP5 (VDDP-IN) and
TP6 (VDDI), no jumper is required on J1 and J9. The D2 green LED is lit when VDDP is
available.
3.2 SCL and SDA jumpers
The I
2
C -bus signals SDA and SCL supplied to the device under test can be sourced
from either the Fm+ board via CN2 or the tester via CN1. Jumpers J12 and J14 select
the I
2
C bus 1 or bus 2 signals from the Fm+ board, shorting pins 1 to 2 to select I
2
C bus 1
while shorting pins 2 to 3 to select I
2
C bus 2.
3.3 Device reset, interrupt and address pin selection
•
Reset
(U1, pin28), the device is resetting when shorting pin 1 to 2 on jumper J5
•
Interrupt
(U1, pin 32), open-drain interrupt (/INT) output is activated and D1 red LED
is lit when any input state differs from its corresponding Input Port register state, TP1
can be used to monitor the /INT pin 32.
UM10868
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
User manual
Rev. 1 — 23 September 2015
3 of 19
NXP Semiconductors
UM10868
PCAL6524 demonstration board OM13526
•
Address input
(U1, pin 26), jumper J10 is used to select device address as shorting
pins 1 to 2 (VDD, address is 46h), shorting pins 3 to 4 (VSS, address is 44h),
shorting pins 5 to 6 (SDA, address is 42h), shorting pins 7 to 8 (SCL, address is
40h).
3.4 Board layout viewer
Fig 1
shows all jumper locations and labels on PCB.
Fig 1.
PCAL6524 demo board layout and Labels
3.5 Connector pinouts
•
CN1
(10-pin male tester connector) is connected to master which is driving either
I
2
C-bus for PCAL6524 or SPI-bus for PCAL9722. This is easily achieved with third
party development tools from Total Phase (http://www.totalphase.com). There are
two tools called Aardvark and Beagle that direct connect to this board through CN1.
Table 1.
CN1 10-pin tester connector
CN1 Pin #
Function
Board connection
1
2,10
3
4, 6
5
7
8
9
SCL
GND
SDA
+5V_TSTR
SDOUT (MISO)
SCLK
SDIN (MOSI)
/CS (SS)
U1 pin 29 (PCAL6524)
Ground
U1 pin 30 (PCAL6524)
J13 pin 3
U1 pin 24 (PCAL9722)
U1 pin 29 (PCAL9722)
U1 pin 30 (PCAL9722)
U1 pin 23 (PCAL9722)
Note:
Since SDA and SCL are both connected to the device (U1) under test, the
Aardvark and the Fm+ Development board cannot be used simultaneously. The Beagle,
a bus sniffer, does not have any issues.
•
CN2
(18-pin female connector) can connect directly to the OM13260 Fm+
Development board. This connector provides power, I
2
C signals and other ancillary
signals.
UM10868
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
User manual
Rev. 1 — 23 September 2015
4 of 19
NXP Semiconductors
UM10868
PCAL6524 demonstration board OM13526
Table 2.
CN2 18-pin Fm+ board connector
CN2 Pin #
Function
Board connection
1, 2, 9, 10, 17, 18 GND
3
4
5, 14
6, 13
7, 12
8, 11
15
16
SCL2
SDA1
/INT
RESET
+5V
+3V3
SDA2
SCL1
Ground
SCL Bus 2 to J12 pin 3
SDA Bus 1 to J14 pin 1
Interrupt to U1 pin 32, LED (D1) and TP1 (test point 1)
U1 pin 28 and J5 pin 1
J13 pin 1
J1 pin 3 and J9 pin 1
SDA Bus 2 to J14 pin 3
SCL Bus 1 to J12 pin 1
Note:
The connector on the Fm+ board is a male, shrouded 14 pin type, while the
connector on this 24-bit GPIO board is an 18-pin female. The reason lies with the shroud
around the 14 pin connector. To ensure correct mating of the female with the male, two
pin positions on both of the female sides are grounded.
•
CN3, CN4, CN5
(10-pin male connector) is connected to GPIO target board
(OM13303) which consists of eight LEDs and eight switches and connects directly to
this 24-bit GPIO board through CN3 (I/O of port 0), CN4 (I/O of port 1), CN5 (I/O of
port2). These switches and LEDs on GPIO target board permit easy exercise of the
I/O functionality of the device under test. The LEDs light red when the voltage on that
channel is below VDDP x 0.3V and LEDs light green when the voltage is above
VDDP x 0.7V. The LEDs remain off when the voltage is between those two levels.
Table 3.
CN3, CN4, CN5 10-pin GPIO target board connector
CN[3:5] pin #
Function
Board connection
1
2
3
4
5
6
7
8
9
10
VDDP_IN
GND
P[0:2]_0 (I/O 0)
P[0:2]_1 (I/O 1)
P[0:2]_2 (I/O 2)
P[0:2]_3 (I/O 3)
P[0:2]_4 (I/O 4)
P[0:2]_5 (I/O 5)
P[0:2]_6 (I/O 6)
P[0:2]_7 (I/O 7)
J1 pin 2 and TP5 (test point 5) and by J7 to VDDP (U1 pin
27)
Ground
U1 pin 1 (by J11), pin 9, pin 17
U1 pin 2, pin 10, pin 18
U1 pin 3, pin 11, pin 19
U1 pin 4, pin 12, pin 20
U1 pin 5, pin 13, pin 21
U1 pin 6, pin 14, pin 22
U1 pin 7, pin 15, pin 23 (by J6)
U1 pin 8, pin 16, pin 24 (by J3)
Please note that CN4 and CN5 pins are incorrectly labeled.
The labels show that both
CN4 and CN5 pins are P0_[0:7], the correct labels are P1_[0:7] for CN4 and P2_[0:7] for
CN5. The schematic is correct, only the labels are incorrect.
3.6 All jumpers default setting and test points
Fig 2
shows the PCAL6524 demo board.
•
TP1 (/INT) is connected to interrupt output (U1 pin 32) for probing use.
UM10868
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
User manual
Rev. 1 — 23 September 2015
5 of 19
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