LT1305
Micropower High Power
DC/DC Converter with
Low-Battery Detector
FEATURES
s
s
s
s
s
s
s
DESCRIPTIO
5V at 400mA from 2V Input
Supply Voltage As Low As 1.8V
120µA Quiescent Current
Low-Battery Detector
Low V
CESAT
Switch: 310mV at 2A Typ
Uses Inexpensive Surface Mount Inductors
8-Lead SO Package
The LT
®
1305 is a micropower step-up DC/DC converter
that uses Burst Mode
TM
operation. Similar to the LT1303,
the LT1305 features a 2A internal low-loss switch and can
deliver up to four times the output power of the LT1303.
Quiescent current is only 120µA and the Shutdown pin
further reduces current to 10µA. A low-battery detector
provides an open-collector output that goes low when the
input voltage drops below a preset level. The LT1305 is
available in an 8-pin SO, easing board space requirements.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation
APPLICATI
s
s
s
S
2-Cell and 3-Cell to 5V Conversion
EL Panel Drivers
Portable Instruments
TYPICAL APPLICATI
2-Cell and 3-Cell to 5V/400mA DC/DC Converter
with Low-Battery Detect
L1
10µH
316k
1%
2 TO 3
CELLS
90
D1
LOW BATTERY
GOES LOW AT
V
BAT
= 2.2V
V
IN
= 4.00V
EFFICIENCY (%)
V
IN
LBI
LT1305
SHDN
GND
SW
LBO
100k
301k
1%
+
C1
220µF
412k
1%
SHUTDOWN
FB
PGND
C2
100k
220µF
1%
+
V
OUT
5V
400mA
C1, C2: AVX TPSE227010R0100
D1: MOTOROLA MBRS130LT3
L1: COILCRAFT D03316-103
LT1305 • TA03
U
Efficiency
80
V
IN
= 3.00V
V
IN
= 2.00V
V
IN
= 2.50V
70
60
1
10
100
LOAD CURRENT (mA)
1000
LT1305 • TA02
UO
UO
1
LT1305
ABSOLUTE
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
GND 1
LBO 2
SHDN 3
FB 4
8
7
6
5
PGND
SW
V
IN
LBI
V
IN
Voltage .............................................................. 10V
SW1 Voltage ............................................................ 25V
FB Voltage ............................................................... 10V
Shutdown Voltage ................................................... 10V
LBO Voltage ............................................................. 10V
LBI Voltage .............................................................. 10V
Maximum Power Dissipation ............................. 500mW
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LT1305CS8
S8 PART MARKING
1305
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 100°C,
θ
JA
= 80°C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
I
Q
V
IN
PARAMETER
Quiescent Current
Input Voltage Range
CONDITIONS
T
A
= 25°C, V
IN
= 2.0V, unless otherwise noted.
MIN
q
q
q
TYP
120
7
MAX
200
15
UNITS
µA
µA
V
V
V
SHDN
= 0.5V, V
FB
= 2V
V
SHDN
= 1.8V
1.8
2.0
1.22
1.55
1.24
6
7
1.26
12.5
20
185
95
0.15
280
10
2.35
2.50
2.15
1.24
7
0.11
0.1
1.27
20
0.4
5
0.5
Feedback Voltage
Comparator Hysteresis
Feedback Pin Bias Current
Oscillator Frequency
Oscillator TC
DC
t
ON
V
CESAT
Maximum Duty Cycle
Switch On Time
Output Line Regulation
Switch Saturation Voltage
Switch Leakage Current
Peak Switch Current
Current Limit Not Asserted
1.8V < V
IN
< 6V
I
SW
= 1A
V
SW
= 5V, Switch Off
V
IN
= 2V
V
FB
= 1V
Current Limit Not Asserted
q
q
q
120
q
155
0.2
86
5.6
0.06
140
0.1
%/°C
%
µs
%/V
mV
µA
A
A
A
V
nA
V
µA
V
V
µA
µA
µA
75
q
q
q
q
1.35
1.20
1.15
1.21
2
V
IN
= 5V
LBI Trip Voltage
LBI Input Bias Current
LBO Output Low
LBO Leakage Current
V
SHDNH
V
SHDNL
I
SHDN
Shutdown Pin High
Shutdown Pin Low
Shutdown Pin Bias Current
V
SHDN
= 5V
V
SHDN
= 2V
V
SHDN
= 0V
q
q
q
(Note 2)
V
LBI
= 1V
I
LOAD
= 100µA
V
LBI
= 1.3V, V
LBO
= 5V
q
q
q
q
q
1.8
8.0
3.0
0.1
20
1
The
q
denotes specifications which apply over the 0°C to 70°C operating
temperature range.
Note 1:
Hysteresis specified is DC. Output ripple may be higher if output
capacitance is insufficient or capacitor ESR is excessive.
Note 2:
Low-battery detector comparator is inoperative when device is in
shutdown.
2
U
V
mV
nA
kHz
W
U
U
W W
W
LT1305
TYPICAL PERFORMANCE CHARACTERISTICS
Switch On Time
8
7
160
150
140
130
120
110
DUTY CYCLE (%)
ON TIME (µs)
6
5
4
3
2
–50
FREQUENCY (kHz)
– 25
0
25
50
TEMPERATURE (°C)
Quiescent Current
200
190
SWITCH OFF
V
IN
= 2V
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
180
170
160
150
140
130
120
110
100
–50
PEAK SWITCH CURRENT (A)
–25
25
50
0
TEMPERATURE (°C)
LBI Pin Bias Current
20
18
16
14
12
10
8
6
4
2
0
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
14
12
10
8
6
4
2
0
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
FEEDBACK VOLTAGE (V)
BIAS CURRENT (nA)
BIAS CURRENT (nA)
U W
75
LT1305 • G01
Oscillator Frequency
200
190
180
170
100
95
90
85
80
75
70
65
60
55
–25
25
50
0
TEMPERATURE (°C)
75
100
Maximum Duty Cycle
100
100
–50
50
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
LT1305 • G02
LT1305 • G03
Quiescent Current
500
T
A
= 25°C
SWITCH OFF
400
2.4
2.2
2.0
1.8
1.6
1.4
1.2
Current Limit
300
200
100
0
75
100
0
2
6
4
INPUT VOLTAGE (V)
8
10
LT1305 • G05
1.0
– 50
–25
50
25
0
TEMPERATURE (˚C)
75
100
LT1305 • G04
LT1305 • G06
FB Pin Bias Current
20
18
16
1.250
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
FB Voltage
1.200
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
LT1305 • G07
LT1305 • G08
LT1305 • G09
3
LT1305
TYPICAL PERFORMANCE CHARACTERISTICS
Low-Battery Detect Trip Point
1.250
1.245
1.240
SWITCH SATURATION VOLTAGE (mV)
350
300
250
200
150
100
50
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)
LT1305 • F12
SWITCH SATURATION VOLTAGE (mV)
LBI VOLTAGE (V)
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
PI FU CTIO S
GND (Pin 1):
Signal Ground. Tie to PGND under the
package.
LBO (Pin 2):
Open-Collector Output of Comparator C3.
Can sink 100µA. High impedance when device is in shut-
down.
SHDN (Pin 3):
Shutdown. Pull high to shut down the
LT1305. Ground for normal operation.
FB (Pin 4):
Feedback Input. Connects to main comparator
C1 input.
LBI (Pin 5):
Low-Battery Comparator Input. When voltage
on this pin is below 1.24V, LBO is low.
V
IN
(Pin 6):
Supply Pin. Must be bypassed with a large
value capacitor to gound. Keep bypass within 0.2" of the
device.
SW (Pin 7):
Switch Pin. Connect inductor and diode here.
Keep layout short and direct to minimize radio frequency
interference.
PGND (Pin 8):
Power Ground. Tie to signal ground (pin 1)
under the package. Bypass capacitor from V
IN
should be
tied directly to PGND within 0.2" of the device.
4
U W
LT1305 • G10
Switch Saturation Voltage
400
T
A
= 25°C
300
Switch Saturation Voltage
I
SW
= 1A
250
200
150
100
50
0
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
LT1305 • G13
U
U
U
LT1305
BLOCK DIAGRAM
V
IN
+
C5
6
C2
4
FB
–
C1
OFF
OSCILLATOR
A3
DRIVER
Q2
1×
Q1
160×
R2
REFERENCE
1.24V
+
–
C3
+
GND
1
5
LBI
2
LBO
SHUTDOWN
3
8
PGND
Figure 1. LT1305 Block Diagram
OPERATION
Operation of the LT1305 is best understood by referring to
the Block Diagram in Figure 1. When C1’s negative input,
related to the output voltage by the appropriate resistor-
divider ratio, is higher than the 1.24V reference voltage,
C1’s output is low. C2, A3 and the oscillator are turned off,
drawing no current. Only the reference and C1 consume
current, typically 120µA. When C1’s negative input drops
below 1.24V and overcomes C1’s 6mV hysteresis, C1’s
output goes high, enabling the oscillator, current compara-
tor C2 and driver A3. Quiescent current increases to 2mA
as the device goes into active switching mode. Q1 then
turns on in controlled saturation for nominally 6µs or until
current comparator C2 trips, whichever comes first. The
switch then turns off for approximately 1.5µs, then turns on
again. The LT1305’s switching causes current to alter-
nately build up in L1 and dump into output capacitor C4 via
D1, increasing the output voltage. When the output is high
enough to cause C1’s output to go high, switching action
ceases. Capacitor C4 is left to supply current to the load
until V
OUT
decreases enough to force C1’s output high, and
the entire cycle repeats. Figure 2 details relevant wave-
forms. C1’s cycling causes low-to-mid-frequency ripple
voltage on the output. Ripple can be reduced by making the
output capacitor large. The 220µF unit specified results in
ripple of 50mV to 100mV on the 5V output. Paralleling two
capacitors will decrease ripple by approximately 50%.
V
OUT
100mV/DIV
AC COUPLED
V
SW
5V/DIV
I
L
1A/DIV
Figure 2. Burst Mode Operation
–
R1
HYSTERETIC
COMPARATOR
+
W
L1
V
IN
SW
D1
+
C4
7
CURRENT
COMPARATOR
36mV
R1
3Ω
LT1305 • F01
U
50µs/DIV
LT1305 • F02
5
FPGA/CPLD
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