Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
2.5V or 3.3V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to V
SSQ
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Three chip enables for depth expansion and address
pipeline
Address, data and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write
pass-through capability allows written data available at the
output for the immediately next Read cycle. This device also
incorporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
The CY7C1327A/GVT71256G18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PC™ systems and for systems that benefit from a wide syn-
chronous data bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The
CY7C1327A/GVT71256G18
SRAM
integrates
262,144x18 SRAM cells with advanced synchronous periph-
Selection Guide
7C1327A-166
71256G18-3
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
3.5
425
10
7C1327A-150
71256G18-4
3.8
400
10
7C1327A-133
71256G18-5
4.0
375
10
7C1327A-117
71256G18-6
4.0
350
10
Cypress Semiconductor Corporation
Document #: 38-05129 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised November 13, 2002
CY7C1327A/GVT71256G18
256K x 18 (CY7C1327A/GVT71256G18) Functional Block Diagram
[1]
UPPER BYTE
WRITE
WEH#
BWE#
D
Q
WEL#
GW#
CE#
CE2
CE2#
ZZ
OE#
ADSP#
Power Down Logic
LOWER BYTE
WRITE
D
Q
hi byte write
Output Buffers
lo byte write
OUTPUT
REGISTER
ENABLE
D
Q
D
Q
Input
Register
A17-A2
ADSC#
Address
Register
256K x 9 x 2
SRAM Array
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
D
Q
DQ1-
DQ16,
DQP1,
DQP2
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05129 Rev. *A
Page 2 of 16
CY7C1327A/GVT71256G18
Pin Configurations
100-Pin TQFP
Top View
A6
A7
CE
CE
2
NC
NC
WEH
WEL
CE
2
V
CC
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
V
CCQ
V
SSQ
NC
NC
DQ9
DQ10
V
SSQ
V
CCQ
DQ11
DQ12
NC
V
CC
NC
V
SS
DQ13
DQ14
V
CCQ
V
SSQ
DQ15
DQ16
DQP2
NC
V
SSQ
V
CCQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1327A/GVT71256G18
(256K X 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
NC
V
CCQ
V
SSQ
NC
DQP1
DQ8
DQ7
V
SSQ
V
CCQ
DQ6
DQ5
V
SS
NC
V
CC
ZZ
DQ4
DQ3
V
CCQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
CCQ
NC
NC
NC
Document #: 38-05129 Rev. *A
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A15
A14
A13
A12
A11
A16
A17
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 16
CY7C1327A/GVT71256G18
Pin Configurations
(continued)
119-Ball Bump BGA
256Kx18—CY7C1327A/GVT71256G18
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
CCQ
NC
NC
DQ9
NC
V
CCQ
NC
DQ12
V
CCQ
NC
DQ14
V
CCQ
DQ18
NC
NC
NC
V
CCQ
2
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
V
CC
DQ13
NC
DQ15
NC
DQP2
A5
A10
NC
3
A4
A3
A2
V
SS
V
SS
V
SS
BWH
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A11
NC
4
ADSP
ADSC
V
CC
NC
CE
OE
ADV
GW
V
CC
CLK
NC
BWE
A1
A0
V
CC
NC
NC
5
A8
A9
A12
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWL
V
SS
V
SS
V
SS
NC
A14
NC
6
A16
CE2
A15
DQ”P1
NC
DQ7
NC
DQ5
V
CC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
7
V
CCQ
NC
NC
NC
DQ8
V
CCQ
DQ6
NC
V
CCQ
DQ4
NC
V
CCQ
NC
DQ1
NC
ZZ
V
CCQ
Pin Descriptions
BGA Pins
QFP Pins
Pin
Name
Type
Description
4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A17
Input-
Addresses: These inputs are registered and must meet the set-up
5A, 6A, 3B, 5B, 33, 32, 100, 99,
Synchronous and hold times around the rising edge of CLK. The burst counter
2C, 3C, 5C, 6C, 82, 81, 80, 48,
generates internal addresses associated with A0 and A1, during
2R, 6R, 2T, 3T, 47, 46, 45, 44,
burst cycle and wait cycle.
5T, 6T
49, 50
5L, 3G
93, 94
WEL,
WEH
Input-
Byte Write Enables: A byte write enable is LOW for a Write cycle
Synchronous and HIGH for a Read cycle. WEL controls DQ1–DQ8 and DQP1.
WEH controls DQ9–DQ16 and DQP2. Data I/O are high-imped-
ance if either of these inputs are LOW, conditioned by BWE being
LOW.
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge of
CLK.
Input-
Global Write: This active LOW input allows a full 18-bit Write to
Synchronous occur independent of the BWE and WEn lines and must meet the
set-up and hold times around the rising edge of CLK.
Input-
Clock: This signal registers the addresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet set-up and hold times around the clock’s rising
edge.
4M
87
BWE
4H
88
GW
4K
89
CLK
Document #: 38-05129 Rev. *A
Page 4 of 16
CY7C1327A/GVT71256G18
Pin Descriptions
(continued)
BGA Pins
4E
6B
2B
4F
4G
QFP Pins
98
92
97
86
83
Pin
Name
CE
CE2
CE2
OE
ADV
Type
Description
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
Input-
Chip Enable: This active LOW input is used to enable the device.
Synchronous
input-
Chip Enable: This active HIGH input is used to enable the device.
Synchronous
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no
address advance).
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and a
Read cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to
Synchronous be deselected or selected along with new external address to be
registered. A Read or Write cycle is initiated depending upon write
control inputs.
Input-
Static
Input-
Asynchro-
nous
Input/
Output
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
Snooze: This active HIGH input puts the device in low power con-
sumption standby mode. For normal operation, this input has to be
either LOW or NC (No Connect).
Data Inputs/Outputs: Low Byte is DQ1–DQ8. HIgh Byte is
DQ9–DQ16. Input data must meet set-up and hold times around
the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2
is parity bit for DQ9–DQ16.
Power Supply: +3.3V –5% and +10%
Ground: GND
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
7T
64
ZZ
7P, 6N, 6L, 7K, 58, 59, 62, 63,
6H, 7G, 6F, 7E, 68, 69, 72, 73, 8,
1D, 2E, 2G, 1H, 9, 12, 13, 18, 19,
2K, 1L, 2M, 1N
22, 23
6D, 2P
4C, 2J, 4J, 6J,
4R
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
74, 24
15, 41,65, 91
17, 40, 67, 90
DQ1–
DQ16
DQP1,
DQP2
V
CC
V
SS
Input/
Output
Supply
Ground
1A, 7A, 1F, 7F, 4, 11, 20, 27, 54,
1J, 7J, 1M, 7M,
61, 70, 77
1U, 7U
5, 10, 21, 26, 55,
60, 71, 76
1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16,
2D, 4D, 7D, 1E, 25, 28-30, 38,
6E, 2F, 1G, 6G, 39, 42, 43, 51-
2H, 7H, 3J, 5J, 53, 56, 57, 66,
1K, 6K, 2L, 4L, 75, 78, 79, 80,
7L, 6M, 2N, 7N,
95, 96
1P, 6P, 1R, 5R,
7R, 1T, 4T, 2U,
3U, 4U, 5U, 6U
V
CCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to V
CC
)
V
SSQ
NC
I/O Ground
-
Output Buffer Ground: GND
No Connect: These signals are not internally connected.
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