AS3729B
8A Power Stage
General Description
The AS3729B is a companion power stage, intended to be used
with AS372x products.
It cannot be used without a DC/DC controller. It contains the
power FETs for 2 phases and is capable to handle output
currents of 4A per phase.
Ordering Information
and
Content Guide
appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS3729B, 8A Power Stage are listed
below:
Figure 1:
Added Value of Using AS3729B
Benefits
•
Support for single or dual phase operation
•
2 x 4A output stages are running up to
2.7MHz
•
Over-temperature protection
•
Cost effective, small package
Features
•
2 phases with separate control input
•
Separate power NMOS & PMOS for 4A per phase
•
Separate coil current feedback per phase
•
Stand-Alone zero-crossing operation
•
Integrated temperature monitoring
•
WL-CSP16: 1.615mm x 1.615mm, 0.4mm pitch
Applications
This device is a high current dual-phase DC/DC and ideal for:
•
Mobile phones
•
Tablets
•
Notebooks
ams Datasheet
[v1-03] 2015-Sep-28
Page 1
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AS3729B −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS3729B Block Diagram
VSUP
VSUP
clk
PWM
Logic
TEMP
PWM
ov_curr
CTRL2
CTRL1
CTRL1
Pgate
Isense
LX1
1uH
47uF
Ngate
Zcomp
Vov_current
RCSNS
Logic
ramp
S
Current sense
PVSS
VRef
error ota
FB
VSS
AS3729B Block Diagram:
This figure shows the block diagram of the DC/DC controller inside the Main PMIC and
the AS3729B Power Stage with all relevant system components.
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ams Datasheet
[v1-03] 2015-Sep-28
AS3729B −
Pin Assignment
Pin Assignment
Figure 3:
16 Balls WL-CSP with 0.4mm Pitch
Pin Assignments:
Shows the top view
pin assignment of the AS3729B
Pin A1
indicator
A1
CTRL1
A2
VSUP
A3
LX1
A4
PVSS
B1
TEMP
B2
VSUP
B3
LX1
B4
PVSS
C1
AGND
C2
VSUP
C3
LX2
C4
PVSS
D1
CTRL2
D2
VSUP
D3
LX2
D4
PVSS
Figure 4:
Pin Description
Pin Number
A1
B1
C1
D1
A2, B2
C2, D2
A3, B3
C3, D3
A4, B4
C4, D4
Pin Name
CTRL1
TEMP
AGND
CTRL2
VSUP
VSUP
LX1
LX2
PVSS
PVSS
Description
Control IO for phase 1
On/Off control and temperature feedback
Analog ground
Control IO for phase 2
Phase 1 positive supply terminal
Phase 2 positive supply terminal
Phase 1 switching output to coil
Phase 2 switching output to coil
Phase 1 negative supply terminal
Phase 2 negative supply terminal
ams Datasheet
[v1-03] 2015-Sep-28
Page 3
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AS3729B −
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under
Electrical
Characteristics
is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 5:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
Supply voltage to ground 5V
pins
Supply voltage to ground 3V
pins
Voltage difference between
ground terminals
Input current
(latch-up immunity)
-0.5
-0.5
-0.5
-100
7.0
5.0
0.5
100
V
V
V
mA
Applicable for pins
VSUPx, LXx, CTRLx
Applicable for pin
TEMP
Applicable for pins
PVSS, AGND
Norm: JEDEC JESD78
Continuous Power Dissipation (T
A
= 70°C)
P
T
Continuous power dissipation
1
W
P
T
(1)
for WL-CSP16 package
(R
THJA
~ 55K/W)
Electrostatic Discharge
ESD
HBM
Electrostatic discharge HBM
±2
kV
Norm:
JEDEC JESD22-A114F
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ams Datasheet
[v1-03] 2015-Sep-28
AS3729B −
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Temperature Ranges and Storage Conditions
T
A
R
THJA
T
J
T
STRG
T
BODY
RH
NC
MSL
Operating temperature
Junction to ambient thermal
resistance
Junction temperature
Storage temperature range
Package body temperature
Relative humidity
(non condensing)
Moisture sensitivity level
5
1
-55
125
125
260
85
-40
85
°C
°C/W
°C
°C
°C
%
Represents an unlimited floor
life time
Norm IPC/JEDEC J-STD-020
(2)
R
THJA
typ. 55K/W
Note(s) and/or Footnote(s):
1. Depending on actual PCB layout and PCB used
2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”
ams Datasheet
[v1-03] 2015-Sep-28
Page 5
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