EDI88128C
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s
Access Times of 70, 85, 100ns
s
Available with Single Chip Selects (EDI88128) or Dual Chip
Selects (EDI88130)
s
2V Data Retention (LP Versions)
s
CS and OE Functions for Bus Control
s
TTL Compatible Inputs and Outputs
s
Fully Static, No Clocks
s
Organized as 128Kx8
s
Industrial, Military and Commercial Temperature Ranges
s
Thru-hole and Surface Mount Packages JEDEC Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic ZIP (Package 100)
• 32 lead Ceramic SOJ (Package 140)
s
Single +5V (±10%) Supply Operation
The EDI88128C is a high speed, high performance, Monolithic
CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional chip
select line (CS
2
) which will automatically power down the device
when proper logic levels are applied.
The second chip select line (CS
2
) can be used to provide system
memory security during power down in non-battery backed up
systems and simplifiy decoding schemes in memory banking
where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional in-
put-output lines to provide simultaneous access to all bits in a
word. An automatic power down feature permits the on-chip
circuitry to enter a very low standby mode and be brought back
into operation at a speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a 2V data
retention function for battery back-up opperation. Military prod-
uct is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
PIN DESCRIPTION
32 DIP
32 SOJ
32 ZIP
I/O
0-7
A
0-16
WE
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V
±10%)
Ground
Not Connected
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
TOP VIEW
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
V
CC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
CS
1
, CS
2
OE
V
CC
V
SS
NC
BLOCK DIAGRAM
Memory Array
A
Ø-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
1
CS
2
OE
* Pin 30 is NC for 88128 or CS
2
for 88130.
July 1999 Rev. 13
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
°C
°C
°C
°C
W
mA
°C
-0.5 to 7.0
Unit
V
OE
X
X
X
H
L
X
CS
1
H
X
X
L
L
L
CS
2
X
L
L
H
H
H
WE
X
X
X
H
H
L
TRUTH TABLE
Mode
Standby
Standby
Output Deselect
Output Deselect
Read
Write
Output
High Z
High Z
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc
3
Icc
2
, Icc
3
Icc
1
Icc
1
Icc
1
Icc
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
Vcc +0.5
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C)
Parameter
Address Lines
Input/Output Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
Max
12
14
Unit
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= +25°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
, CS
1
≥
V
IH
and/or CS
2
≤
V
IL
WE, CS
1
= V
IL
, I
I/O
= 0mA, Min Cycle
CS
2
= V
IH
(70-85ns)
(100ns)
C
LP
Conditions
Min
-5
-10
—
—
—
—
—
—
2.4
1
—
—
—
Typ
—
—
Max
+5
+10
120
110
10
5
1
0.4
—
µA
µA
mA
mA
mA
mA
mA
V
V
Units
CS
1
≥
V
IH
and/or CS
2
≤
V
IL
, V
IN
≥
V
IH
or
≤
V
IL
CS
1
≥
V
CC
-0.2V and/or CS
2
≤
Vcc +0.2V
V
IN
≥
Vcc -0.2V or V
IN
≤
0.2V
I
OL
= 2.1mA
I
OH
= -1.0mA
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
EDI88128C
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
ELQV
t
SHQV
t
ELQX
t
SHQX
t
EHQZ
t
SLQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
ACS
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
0
0
30
3
3
0
0
3
25
0
0
30
30
30
70ns
Min
70
70
70
70
3
3
0
0
3
30
0
0
30
30
30
Max
Min
85
85
85
85
3
3
0
0
3
50
30
30
85ns
Max
Min
100
100
100
100
100ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
NOTE:
For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Parameter
Write Cycle Time
Chip Select to End of Write
Symbol
JEDEC
Alt.
t
AVAV
t
ELWH
t
ELEH
t
SHWH
t
SHSL
t
AVWL
t
AVEL
t
AVSH
t
AVWH
t
WLWH
t
WLEH
t
WLSL
t
WHAX
t
EHAX
t
SLAX
t
WHDX
t
EHDX
t
SLDX
t
WLQZ
t
DVWH
t
DVEH
t
DVSL
t
WHQX
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
70ns
Min
70
60
60
60
60
0
0
0
60
35
35
35
5
5
5
0
0
0
0
35
35
35
5
30
Max
Min
85
75
75
75
75
0
0
0
75
70
70
70
5
5
5
0
0
0
0
40
40
40
5
35
85ns
Max
Min
100
85
85
85
85
0
0
0
85
80
80
80
5
5
5
0
0
0
0
40
40
40
5
40
100ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
EDI88128C
FIG. 2
TIMING WAVEFORM - READ CYCLE
t
AVAV
ADDRESS
t
AVQV
CS
1
t
AVAV
ADDRESS
t
ELQV
t
ELQX
CS
2
ADDRESS 2
t
EHQZ
ADDRESS 1
t
SHQV
t
SHQX
OE
DATA 2
t
SLQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
t
GLQV
t
GLQX
DATA I/O
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE 1
ADDRESS
t
AVAV
t
AVWH
t
WLWH
t
AVWL
WE
t
WHAX
CS
1
t
ELWH
CS
2
t
SHWH
DATA IN
t
DVWH
t
WHQX
t
WHDX
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4
WRITE CYCLE2
t
AVAV
ADDRESS
WRITE CYCLE 3
WS32K32-XHX
ADDRESS
t
AVAV
t
SLAX
t
AVEL
WE
t
WLEH
t
EHAX
WE
t
AVSH
t
WLSL
t
ELEH
CS
1
t
SHSL
CS
1
CS
2
CS
2
t
DVEH
DATA IN
DATA VALID
t
EHDX
DATA IN
t
DVSL
DATA VALID
t
SLDX
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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