White Electronic Designs
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
Access Times of 70, 85, 100ns
Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
2V Data Retention (LP Versions)
CS# and OE# Functions for Bus Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 128Kx8
Industrial, Military and Commercial Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
Single +5V (±10%) Supply Operation
EDI88128C
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bi-
directional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
V
CC
V
SS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 V
CC
31 A15
30 NC/CS2*
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
BLOCK DIAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
April 2005
Rev. 17
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
1
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White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
-0.5 to 7.0
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
Unit
V
°C
°C
°C
°C
W
mA
°C
OE# CS1# CS2# WE#
Mode
X
H
X
X
Standby
X
X
L
X
Standby
X
X
L
X
Output Deselect
H
L
H
H
Output Deselect
L
L
H
H
Read
X
L
H
L
Write
EDI88128C
TRUTH TABLE
Output
High Z
High Z
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Icc1
Icc1
Icc1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+0.5
+0.8
Unit
V
V
V
V
CAPACITANCE
T
A
= +25°C
Symbol
Parameter
Address Lines
C
I
Input/Output Lines
C
O
Condition
V
IN
= V
CC
or V
SS
, f = 1.0MHz
V
OUT
= V
CC
or V
SS
, f = 1.0MHz
Max Unit
12 pF
14 pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
V
CC
= 5V, -55°C ≤ T
A
≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol Conditions
V
IN
= 0V to V
CC
I
LI
I
LO
V
I/O
= 0V to V
CC
, CS1# ≥ V
IH
and/or CS2# ≤ V
IL
WE#, CS1# = V
IL
, I
I/O
= 0mA, Min Cycle
(70-85ns)
I
CC1
CS2# = V
IH
(100ns)
I
CC2
CS1# ≥ V
IH
and/or CS2# ≤ V
IL
, V
IN
≥ V
IH
or ≤ V
IL
CS1# ≥ V
CC
-0.2V and/or CS2# ≤ V
CC
+0.2V
C
I
CC3
V
IN
≥ V
CC
-0.2V or V
IN
≤ 0.2V
LP
V
OL
I
OL
= 2.1mA
V
OH
I
OH
= -1.0mA
Min
-5
-10
—
—
—
—
—
—
2.4
Typ
—
—
Max
+5
+10
120
110
10
5
1
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
V
V
1
—
—
—
NOTE: DC test conditions : V
IL
= 0.3V, V
IH
= V
CC
-0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC Characteristics – Read Cycle
V
CC
= 5V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
1. This parameter is guaranteed by design but not tested.
EDI88128C
Symbol
JEDEC
t
AVAV
t
AVQV
t
ELQV
t
SHQV
t
ELQX
t
SHQX
t
EHQZ
t
SLQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
Alt.
t
RC
t
AA
t
ACS
t
ACS
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
Min
70
70ns
Max
70
70
70
3
3
30
30
3
25
0
0
30
0
0
3
3
3
Min
85
85ns
Max
85
85
85
3
3
30
30
3
30
30
0
0
Min
100
100ns
Max
100
100
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
50
30
AC Test Conditions
Figure 1
Figure 2
Vcc
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
Q
255Ω
30pF
Q
255Ω
5pF
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC CHARACTERISTICS – WRITE CYCLE
V
CC
= 5V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Write Cycle Time
Chip Select to End of Write
Symbol
JEDEC
t
AVAV
t
ELWH
t
ELEH
t
SHWH
t
SHSL
t
AVWL
t
AVEL
t
AVSH
t
AVWH
t
WLWH
t
WLEH
t
WLSL
t
WHAX
t
EHAX
t
SLAX
t
WHDX
t
EHDX
t
SLDX
t
WLQZ
t
DVWH
t
DVEH
t
DVSL
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
Min
70
60
60
60
60
0
0
0
60
35
35
35
5
5
5
0
0
0
0
35
35
35
5
30
70ns
Max
Min
85
75
75
75
75
0
0
0
75
70
70
70
5
5
5
0
0
0
0
40
40
40
5
35
85ns
Max
Min
100
85
85
85
85
0
0
0
85
80
80
80
5
5
5
0
0
0
0
40
40
40
5
EDI88128C
100ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
40
ns
ns
ns
ns
ns
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 2 – TIMING WAVEFORM — READ CYCLE
t
AVAV
ADDRESS
EDI88128C
t
AVQV
CS1#
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
t
ELQV
t
ELQX
CS2
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
t
SHQV
t
SHQX
OE#
t
SLQZ
t
GLQV
t
GLQX
DATA I/O
READ CYCLE 2 (WE# HIGH)
t
GHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
FIGURE 3 – WRITE CYCLE 1
t
AVAV
ADDRESS
t
AVWL
WE#
t
AVWH
t
WLWH
t
WHAX
CS1#
t
ELWH
CS
2
t
SHWH
DATA IN
t
DVWH
DATA VALID
t
WHQX
t
WHDX
t
WLQZ
DATA OUT
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE 2
t
AVAV
ADDRESS
WRITE CYCLE 3
t
AVAV
ADDRESS
t
AVEL
WE#
t
WLEH
t
EHAX
WE#
t
AVSH
t
WLSL
t
SLAX
t
ELEH
CS
1#
t
SHSL
CS1#
CS
2
CS2
t
DVEH
DATA IN
DATA VALID
t
EHDX
DATA IN
t
DVSL
DATA VALID
t
SLDX
WRITE CYCLE 2 - EARLY WRITE, CS
1#
CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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