NJM2267
DUAL VIDEO 6dB AMPLIFIER WITH 75Ω DRIVER
■
GENERAL DESCRIPTION
NJM2267
is a dual video 6dB amplifier with 75Ω drivers for S-VHS
VCRs, HI-BAND VCRs, etc..Each channel has clamp function that
fixes DC level of video signal and 75Ω drivers to be connected to TV
monitors directly. Further more it has sag corrective circuits that
prevent the generation of sag with smaller capacitance than ever.
Its operating supply voltage is 4.85 to 9V and bandwidth is 7MHz.
■
FEATURES
●
Wide Operating Voltage (4.85V to 9.0V)
●
Dual Channel
●
Internal Clamp Function
●
Internal Driver Circuit For 75Ω Load
●
SAG Corrective Function
●
Wide Frequency Range (7MHz)
●
Low Operating Current 14.0mA (Dual)
●
Package Outline DIP8, DMP8, SSOP8
●
Bipolar Technology
■
APPLICATIONS
●VCR,
Video Camera, TV, Video Disc Player.
■
BLOCK DIAGRAM
■
PACKAGE OUTLINE
NJM2267D
NJM2267M
NJM2267V
Ver.2016-06-06
-1-
NJM2267
■
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Power Dissipation
SYMBOL
V
P
D
+
(Ta=25°C)
RATINGS
10
(DIP8) 500
(DMP8) 300
(SSOP8) 250
-40 to +85
-40 to +125
UNIT
V
mW
mW
mW
Operating Temperature Range
Storage Temperature Range
T
opr
T
stg
°C
°C
(V
+
=5V, Ta=25±2°C)
■
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Current
Voltage Gain
Frequency Characteristics
Differential Gain
Differential Phase
Crosstalk
Gain Offset
Input Clamp Voltage
SAG Terminal Gain
SYMBOL
I
CC
G
V
G
f
DG
DP
CT
G
CH
V
CL
G
SAG
No Signal
V
IN
=1MHz, 1V
P-P
Sinewave
V
IN
=1V
P-P
, Sinewave, 7MHz / 1MHz
V
IN
=1V
P-P
, Staircase
V
IN
=1V
P-P
, Staircase
V
IN
=4.43MHz, 1V
P-P
, Sinewave
V
IN
=1MHz, 1V
P-P
, G
CH
=V
OUT1
-V
OUT2
TEST CONDITION
MIN.
-
5.7
-
-
-
-
-
1.79
35
TYP.
14.0
6.2
-
1.0
1.0
-70
-
1.91
45
MAX.
18.2
6.7
±1.0
3.0
3.0
-
±0.5
2.03
-
UNIT
mA
dB
dB
%
deg
dB
dB
V
dB
■
APPLICATION
Oscillation Prevention
It is much effective to insert LPF (Cutoff Frequency 70MHz) under light loading conditions (RL » 1kΩ)
-2-
Ver.2016-06-06
NJM2267
■
TERMINAL FUNCTION
PIN No.
1
PIN NAME
Input
Clamp
Terminal
(V
+
=5.0V, Ta=25°C)
EQUIVALENT CIRCUIT
FUNCTIONS
Input terminal of 1V
P-P
composite signal or Y signal.
Clamp level is 1.9V
SYMBOL
V
IN1
2
3
GND
SAG
correction
GND
V
SAG1
Ground
SAG caused by a coupling capacitor of the output can be
prevented by connecting this terminal with the output terminal
through an external capacitor.(see block diagram)
When SAG correcting function is not necessary, this terminal
must be connected with pin
“4”
directly.
4
Video
Output1
V
OUT1
Output terminal that can drive 75Ω line.
5
Video
Output2
V
OUT2
Output terminal that can drive 75Ω line.
6
SAG
correction
V
SAG2
SAG caused by a coupling capacitor of the output can be
prevented by connecting this terminal with the output terminal
through an external capacitor.(see block diagram)
When SAG correcting function is not necessary, this terminal
must be connected with pin
“5”
directly.
7
8
V
Input
Clamp
Terminal
+
V
V
IN2
+
Supply Voltage
Input terminal of 1V
P-P
composite signal or Y signal.
Clamp level is 1.9V
Ver.2016-06-06
-3-
NJM2267
■
TEST CIRCUIT
■
TEST METHODES
PARAMETER
Supply Current
Voltage Gain
Frequency
Characteristic
Differential Gain
Differential Phase
Crosstalk
Gain Offset
Input Clamp Voltage
SYMBOL
S1
I
CC
G
V
G
f
DG
DP
CT
G
CH
V
CL
G
SAG
H
H
H
H
H
H
H
H
H
H
SWITCH CONDITIONS
S2
H
H
H
H
H
L
H
H
H
H
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
S4
S5
S6
CONDITIONS
7PIN Sink Current
V
OUT1
/ V
IN
, V
OUT2
/ V
IN2
at V
IN1
(V
IN2
)=1MHz, 1V
P-P
, Sinewave
G
V1M
; Voltage Gain at V
IN1
(V
IN2
)=1MHz, 1V
P-P
G
V10M
; Voltage Gain at V
IN1
(V
IN2
)=7MHz, 1V
P-P
G
f
=G
V10M
-G
V1M
Measuring V
OUT3
at V
IN1
=Staircase Signal
Measuring V
OUT3
at V
IN1
=Staircase Signal
V
OUT2
/ V
OUT1
at V
IN1
=4.43MHz, 1V
P-P
, Sinewave
V
OUT1
/ VIN2 at V
IN12
=4.43MHz, 1V
P-P
, Sinewave
G
V1
=V
OUT1
/ V
IN1
, G
V2
=V
OUT2
/ V
IN2
G
CH
=G
V1
-G
V2
Measuring at TP1 (TP2)
TP3 (TP4) Voltage; Vo1A (Vo2A), TP5 (TP6) voltage;
Vso1A (Vso2A)
TP3 (TP4) Voltage; Vo1B(Vo2B), TP5 (TP6) voltage;
Vso1B (Vso2B)
G
SAG
=20log{ (Vo1B-Vo1A) / (Vso1A-Vso1B) }
G
SAG
=20log{ (Vo2B-Vo2A) / (Vso2A-Vso2B) }
SAG Terminal Gain
-4-
Ver.2016-06-06
NJM2267
Clamp
circuit
1. Operation of Sync-tip-clamp
Input circuit will be explained. Sync-tip clamp circuit (below the clamp circuit) operates to keep a sync tip of the minimum
potential of the video signal. Clamp circuit is a circuit of the capacitor charging and discharging of the external input Cin. It is
charged to the capacitor to the external input Cin at sync tip of the video signal. Therefore, the potential of the sync tip is fixed.
And it is discharged charge by capacitor Cin at period other than the video signal sync tip. This is due to a small discharge
current to the IC.
In this way, this clamp circuit is fixed sync tip of video signal to a constant potential from charging of Cin and discharging of
Cin at every one horizontal period of the video signal.
The minute current be discharged an electrical charge from the input capacitor at the period other than the sync tip of video
signals. Decrease of voltage on discharge is dependent on the size of the input capacitor Cin.
If you decrease the value of the input capacitor, will cause distortion, called the H sag. Therefore, the input capacitor
recommend on more than 0.1uF.
charge
current
signal input
Cin
Vin
Clamp circuit
diccharge
current
< Clamp circuit >
A. Cin is large
B. Cin is small (H sag experience)
clamp potential
charge period
discharge period
charge period
clamp potential
charge period
discharge period
charge period
< Waveform of input terminal >
2. Input impedance
The input impedance of the clamp circuit is different at the capacitor discharge period and the charge period.
The input impedance of the charging period is a few k. On the other hand, the input impedance of the discharge period is
several M. Because is a small discharge-current through to the IC.
Thus the input impedance will vary depending on the operating state of the clamp circuit.
3. Impedance of signal source
Source impedance to the input terminal, please lower than 200. A high source impedance, the signal may be distorted. If
so, please to connect a buffer for impedance conversion.
Ver.2016-06-06
-5-
FPGA/CPLD
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