MX29L8100G
8M-BIT [1M x 8/512K x 16] CMOS
SINGLE VOLTAGE 3V ONLY FLASH
SUPER SOLUTION FOR HIGH SPEED EPROM
FEATURES
• Single-supply voltage range 3.0V to 3.6V for read and
write
• Endurance 10 cycles
• Fast access time: 100ns
• Optimized block architecture
- One 16 Kbyte protected block(16K-block)
- Two 8 Kbyte parameter blocks
- One 96 Kbyte main block
- Seven 128 Kbyte main blocks
• Software EEPROM emulation with parameter blocks
• Status register
- For detection of program or erase cycle completion
• Auto Erase operation
- Automatically erases any one of the sectors or the
whole chip
- Erase suspend capability
- Fast erase time: 50ms typical for chip erase
Auto Page Program operation
- Automatically programs and verifies data at specified
addresses
- Internal address and data latches for 128 bytes per
page
Low power dissipation
- 20mA active current
- 20uA standby current
Built-in 128 Bytes/64 words Page Buffer
- Work as SRAM for temporary data storage
- Fast access to temporary data
Low Vcc write inhibit - 1.8V
Industry standard surface mount packaging
- 42 Lead PDIP
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1.0 GENERAL DESCRIPTION
The MX29L8100G is a 8 Mbit, 3.3 V-only Flash memory
organized as a either 1 Mbytesx8 or 512K word x16. For
flexible erase and program capability, the 8 Mbits of data
is divided into 11 sectors of one 16 Kbyte block, two 8
Kbyte parameter blocks, one 96 Kbyte main block, and
seven 128 Kbyte main blocks. To allow for simple in-
system operation, the device can be operated with a single
3.0 V to 3.6 V supply voltage. Since many designs read
from the flash memory a large percentage of the time,
significant power saving is achieved with the 3.0 V VCC
operation.
The MX29L8100G command set is compatible with the
JEDEC single-power-supply flash standard. Commands
are written to the command register using standard mi-
croprocessor write timings. MXIC's flash memory aug-
ments EPROM functionality with an internal state ma-
chine which controls the erase and program circuitry. The
device Status Register provides a convenient way to
monitor when a program or erase cycle is complete, and
the success or failure of that cycle.
Programming the MX29L8100G is performed on a page
basis; 128 bytes of data are loaded into the device and
then programmed simultaneously. The typical Page Pro-
gram time is 5ms.The device can also be reprogrammed
in standard EPROM programmers. Reading data out of
the device is similar to reading from an EPROM or other
flash.
Erase is accomplished by executing the Erase command
sequence. This will invoke the Auto Erase algorithm which
is an internal algorithm that automatically times the erase
pulse widths and verifies proper cell margin. This device
features both chip erase and block erase. Each block
can be erased and programmed without affecting other
blocks. Using MXIC's advanced design technology, no
preprogram is required (internally or externally). As a
result, the whole chip can be typically erased and veri-
fied in as fast as 50 ms.
The device has 128 Bytes built-in page buffer, which can
serve as SRAM. This feature provides a convenient way
to store temporary data for fast read and write.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on ad-
dress and data pin from -1V to VCC +1V.
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MX29L8100G
PIN CONFIGURATIONS
SYMBOL
A0 - A18
Q0 - Q14
Q15/A-1
CE
OE
WE
BYTE
VCC
GND
PIN NAME
Address Input
Data Input/Output
Q15(word mode)/LSB addr(Byte mode)
Chip Enable Input
Output Enable Input
Write Enable
Word/Byte Selection Input
Power Supply Pin (3.0 V - 3.6 V)
Ground Pin
1.1 PINOUTS
42-PDIP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
1.2 MX29L8100G SECTOR ARCHITECTURE
(Byte Mode Addr. A-1 ~ A18)
FFFFFH
FC00
FBFF
FA00
F9FF
F800
F7FF
0
F
0
F
0
F
H
H
H
H
H
H
16-Kbyte BLOCK
8 - K b y t e PA R A M E T E R B L O C K
8 - K b y t e PA R A M E T E R B L O C K
96-Kbyte MAIN BLOCK
(Word Mode Addr. A0 ~ A18)
7FFFFH
7E00
7DFF
7D00
7CFF
7C00
7BFF
0
F
0
F
0
F
H
H
H
H
H
H
16-Kbyte BLOCK
8 - K b y t e PA R A M E T E R B L O C K
8 - K b y t e PA R A M E T E R B L O C K
96-Kbyte MAIN BLOCK
E0000H
DFFFFH
128-Kbyte MAIN BLOCK
C0000H
BFFFFH
128-Kbyte MAIN BLOCK
A0000H
9FFFFH
128-Kbyte MAIN BLOCK
80000H
7FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
00000H
70000H
6FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
50000H
4FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
128-Kbyte MAIN BLOCK
30000H
2FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
128-Kbyte MAIN BLOCK
00000H
MX29L8100G Memory Map
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MX29L8100G Memory Map
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MX29L8100G
MX29L8100G
BLOCK DIAGRAM
CE
OE
WE
BYTE
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
COMMAND INTERFACE
REGISTER
X-DECODER
MX29L8100G
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
(CIR)
ADDRESS
Q15/A-1
A0-A18
LATCH
AND
BUFFER
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PAGE
PROGRAM
DATA LATCH
Q15/A-1
Q0-Q14
I/O BUFFER
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MX29L8100G
Table 1 .PIN DESCRIPTIONS
SYMBOL
A0 - A18
Q0 - Q7
TYPE
INPUT
INPUT/OUTPUT
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle.
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array, status, identifier data, and page buffer
in the appropriate read mode. Float to tri-state when the chip is deselected or
the outputs are disabled.
HIGH-BYTE DATA BUS:Input data during x16 Data-Write operations. Outputs
array, identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected or the outputs are disabled.
Selectes between high-byte data INPUT/OUTPUT (BYTE=HIGH) and LSB
ADDRESS (BYTE=LOW)
BYTE ENABLE:BYTE Low places device in x8 mode. All data is then input or
output on Q0~7 and Q8~14 float. Address Q15/A-1 selectes between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/
A-1 input buffer. Address A0, then becomes the lowest order address.
CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, de-
coders and sense amplifiers. With CE high, the device is deselected and power
consumption reduces to Standby level upon completion of any current program
or erase operations. CE must be low to select the device.
OUTPUT ENABLES: Gates the device's data through the output buffers during
a read cycle. OE is active low.
WRITE ENABLE: Controls writes to the Command Interface Register(CIR).
WE is active low.
DEVICE POWER SUPPLY(3.0 V - 3.6 V)
GROUND
Q8-Q14
INPUT/OUTPUT
Q15/A-1
BYTE
INPUT/OUTPUT
INPUT
CE
INPUT
OE
WE
VCC
GND
INPUT
INPUT
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MX29L8100G
1.3 BUS OPERATION
Flash memory reads, erases and writes in-system via
the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles. These
bus operations are summarized below.
Table2-1 MX29L8100G Bus Operations for Byte-Wide Mode (BYTE=VIL)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
WE
VIH
VIH
X
VIH
VIH
VIL
A0
X
X
X
VIL
VIH
X
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VHH
VHH
X
Q0-Q7
DOUT
High Z
High Z
C2H
85H
DIN
Q8-Q14
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
Q15/A-1
VIL/VIH
X
VIL
VIL
VIL/VIH
NOTES :1.
X can be VIH or VIL for address or control pins.
2. VHH = 11.5V- 12.5V.
3. Q15/A-1=VIL, Q0~Q7=D0~D7 out, Q15/A-1=VIH, Q0~Q7=D8~D15 out
Table2-2 MX29L8100G Bus Operations for Word-Wide Mode (BYTE=VIH)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
WE
VIH
VIH
X
VIH
VIH
VIL
A0
X
X
X
VIL
VIH
X
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VHH
VHH
X
Q0-Q7
DOUT
High Z
High Z
C2H
85H
DIN
Q8-Q14
DOUT
HighZ
HighZ
00H
00H
DIN
Q15/A-1
DOUT
HighZ
HighZ
0B
0B
DIN
NOTES :1.X
can be VIH or VIL for address or control pins.
2. VHH = 11.5V- 12.5V.
1.4 WRITE OPERATIONS
The Command Interface Register (CIR) is the interface
between the microprocessor and the internal chip con-
troller. Device operations are selected by writing specific
address and data sequence into the CIR, using standard
microprocessor write timings. Writing incorrect data value
or writing them in improper sequence will reset the de-
vice to the read mode.(read array or read buffer) Table 3
defines the valid command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) are valid
only while an erase operation is in progress and will be
ignored in other circumstance. There are four read
modes: Read Array, Read Silicon ID, Read Status Regis-
ter, and Read Page Buffer. For Program and Erase
inform the internal state machine that a program or erase
sequence has been requested. During the execution of
program or erase operation, the state machine will con-
trol the program /erase sequence. After the state ma-
chine has completed its task, it will set bit 7 of the Status
Register (SR. 7) to a "1", which indicates that the CIR
can respond to the full command set.
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