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74LVC841APW,118: 产品描述IC TRANSP LATCH 10BIT 24TSSOP; 产品类别逻辑逻辑; 文件大小137KB，共21页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LVC841APW,118概述

IC TRANSP LATCH 10BIT 24TSSOP

74LVC841APW,118规格参数

参数名称	属性值
Brand Name	NXP Semiconductor
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	TSSOP2
包装说明	4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24
针数	24
制造商包装代码	SOT355-1
Reach Compliance Code	compliant
系列	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24
JESD-609代码	e4
长度	7.8 mm
负载电容（CL）	50 pF
逻辑集成电路类型	BUS DRIVER
最大I（ol）	0.024 A
湿度敏感等级	1
位数	10
功能数量	1
端口数量	2
端子数量	24
最高工作温度	125 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装等效代码	TSSOP24,.25
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法	TAPE AND REEL
峰值回流温度（摄氏度）	260
电源	3.3 V
Prop。Delay @ Nom-Sup	8.5 ns
传播延迟（tpd）	11 ns
认证状态	Not Qualified
座面最大高度	1.1 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1.2 V
标称供电电压 (Vsup)	2.7 V
表面贴装	YES
技术	CMOS
温度等级	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	4.4 mm
Base Number Matches	1

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74LVC841A

10-bit transparent latch with 5 V tolerant inputs/outputs;

3-state

Rev. 03 — 24 May 2004

Product data sheet

1. General description

The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and

superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can

handle 5 V. This feature allows the use of these devices as translators in a mixed

3.3 V and 5 V environment.

The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each

latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and

an output enable (pin OE) input are common to all internal latches. The 74LVC841A

consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at

the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch

output will change each time its corresponding D-input changes. When pin LE is LOW the

latches store the information that was present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches

are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the pin OE input does not affect the state of the latches.

2. Features

5 V tolerant inputs/outputs; for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

Inputs accept voltages up to 5.5 V

CMOS low power consumption

Direct interface with TTL levels

Flow-through pin-out architecture

Complies with JEDEC standard JESD8B/JESD36

ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C.

74LVC841APW,118相似产品对比

	74LVC841APW,118	74LVC841ADB-T	74LVC841ABQ,115	74LVC841ADB,112	74LVC841ADB,118	74LVC841AD,118
描述	IC TRANSP LATCH 10BIT 24TSSOP	闭锁 10bit bus interfc latch 3st	IC 10BIT TRANSP LATCH 24DHVQFN	IC 10BIT TRANSP LATCH 24SSOP	IC 10BIT TRANSP LATCH 24SSOP	IC 10BIT TRANSP LATCH 24SOIC
是否Rohs认证	符合	符合	符合	符合	符合	符合
厂商名称	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	TSSOP2	SSOP	QFN	SSOP2	SSOP2	SOP
包装说明	4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24	SSOP,	HVQCCN,	5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24	5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24	7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24
针数	24	24	24	24	24	24
Reach Compliance Code	compliant	unknown	unknown	compliant	compliant	compliant
系列	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24	R-PDSO-G24	R-PQCC-N24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609代码	e4	e4	e4	e4	e4	e4
长度	7.8 mm	8.2 mm	5.5 mm	8.2 mm	8.2 mm	15.4 mm
逻辑集成电路类型	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
湿度敏感等级	1	1	1	1	1	1
位数	10	10	10	10	10	10
功能数量	1	1	1	1	1	1
端口数量	2	2	2	2	2	2
端子数量	24	24	24	24	24	24
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	SSOP	HVQCCN	SSOP	SSOP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
峰值回流温度（摄氏度）	260	260	260	260	260	260
传播延迟（tpd）	11 ns	11 ns	11 ns	11 ns	11 ns	11 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.1 mm	2 mm	1 mm	2 mm	2 mm	2.65 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
标称供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
端子形式	GULL WING	GULL WING	NO LEAD	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.5 mm	0.65 mm	0.65 mm	1.27 mm
端子位置	DUAL	DUAL	QUAD	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30
宽度	4.4 mm	5.3 mm	3.5 mm	5.3 mm	5.3 mm	7.5 mm
Base Number Matches	1	1	1	1	1	1
Brand Name	NXP Semiconductor	-	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor
制造商包装代码	SOT355-1	-	SOT815-1	SOT340-1	SOT340-1	SOT137-1
负载电容（CL）	50 pF	50 pF	-	50 pF	50 pF	50 pF
最大I（ol）	0.024 A	-	-	0.024 A	0.024 A	0.024 A
封装等效代码	TSSOP24,.25	-	-	SSOP24,.3	SSOP24,.3	SOP24,.4
包装方法	TAPE AND REEL	-	-	TUBE	TAPE AND REEL	TAPE AND REEL
电源	3.3 V	-	-	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	8.5 ns	-	-	8.5 ns	8.5 ns	8.5 ns

74LVC841APW,118

74LVC841APW,118概述

74LVC841APW,118规格参数

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74LVC841APW,118相似产品对比

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