74LVT162374
Rev. 4 — 1 October 2018
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω
termination resistors; 3-state
Product data sheet
1. General description
The 74LVT162374 is a high performance BiCMOS product designed for V
CC
operation at 3.3 V.
The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW states of
the output. This design reduces line noise in applications such as memory address drivers, clock
drivers, and bus receivers/transmitters.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The
device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the
clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +12 mA and −12 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Outputs include series resistance of 30 Ω making external resistors unnecessary
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
•
JESD78B Class II exceeds 500 mA
ESD protection:
•
HBM: JESD22-A114F exceeds 2000 V
•
MM: JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVT162374DGG -40 °C to +85 °C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Nexperia
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
4. Functional diagram
47
46
44
43
41
40
38
37
1
1OE
48
1CP
24
2OE
25
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
001aaa254
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
001aac369
Fig. 1.
Logic symbol
nD0
D
nD1
D
nD2
D
nD3
D
Fig. 2.
nD4
D
IEC logic symbol
nD5
D
nD6
D
nD7
D
CP
nCP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
001aac371
Fig. 3.
Logic diagram
74LVT162374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 4 — 1 October 2018
2 / 12
Nexperia
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
V
CC
V
CC
27 Ω
output
27 Ω
001aac372
Fig. 4.
Schematic of each output
5. Pinning information
5.1. Pinning
74LVT162374
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
aaa-029126
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Fig. 5.
Pin configuration SOT362-1 (TSSOP48)
74LVT162374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 4 — 1 October 2018
3 / 12
Nexperia
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7
1OE, 2OE
1CP, 2CP
GND
V
CC
Pin
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Description
data inputs
data inputs
data outputs
data outputs
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
ground (0 V)
supply voltage
6. Functional description
Table 3. Function table
[1]
Operating mode
Load and read register
Hold
Disable outputs
Input
nOE
L
L
L
H
H
[1]
nCP
↑
↑
NC
NC
↑
nDn
l
h
X
X
nDn
Internal
flip-flops
L
H
NC
NC
nDn
Output
nQn
L
H
NC
Z
Z
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
[1]
Conditions
Min
-0.5
-0.5
-0.5
-50
-50
-
-64
-65
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
Unit
V
V
V
mA
mA
mA
mA
°C
74LVT162374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 4 — 1 October 2018
4 / 12
Nexperia
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
Conditions
[2]
Min
Max
+150
Unit
°C
Symbol
T
j
[1]
[2]
Parameter
junction temperature
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
Δt/ΔV
T
amb
supply voltage
input voltage
input transition rise and fall rate
ambient temperature
outputs enabled
Conditions
Min
2.7
0
-
-40
Typ
-
-
-
-
Max
3.6
5.5
10
+85
Unit
V
V
ns/V
°C
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
OH
I
OL
V
OL(pu)
I
I
Parameter
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
power-up LOW-level
output voltage
input leakage current
V
CC
= 3.6 V; I
O
= 1 mA; V
I
= GND or V
CC
[2]
all input pins
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
control pins
V
CC
= 3.6 V; V
I
= V
CC
or GND
I/O data pins; V
CC
= 3.6 V
V
I
= V
CC
V
I
= 0 V
I
OFF
I
BHL
I
BHH
I
BHLO
I
BHHO
I
CEX
I
O(pu/pd)
power-off leakage current
bus hold LOW current
bus hold HIGH current
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
nDn inputs; V
CC
= 3 V; V
I
= 0.8 V
nDn inputs; V
CC
= 3 V; V
I
= 2.0 V
nDn inputs; V
CC
= 3.6 V; V
I
= 0 V to 3.6 V
[4]
nDn inputs; V
CC
= 3.6 V; V
I
= 0 V to 3.6 V
[4]
[3]
-
-
-
75
-75
500
-
-
[5]
-
0.1
-0.4
0.1
135
-135
-
-
50
1
1
-5
±100
-
-
-
-500
125
±100
μA
μA
μA
μA
μA
μA
μA
μA
μA
[3]
-
0.1
±1
μA
[3]
-
0.4
10
μA
V
CC
= 3.0 V; I
OH
= -12 mA
V
CC
= 3.0 V; I
OL
= 12 mA
Conditions
V
CC
= 2.7 V; I
IK
= -18 mA
Min
-
2.0
-
2.0
-
-
-
-
Typ[1]
-0.85
-
-
-
-
-
-
0.1
Max
-1.2
-
0.8
-
0.8
-12
12
0.55
Unit
V
V
V
V
V
mA
mA
V
output high leakage current output in HIGH-state when V
O
> V
CC
;
V
O
= 5.5 V; V
CC
= 3.0 V
power-up/power-down
output current
V
CC
≤ 1.2 V; V
O
= 5.0 V to V
CC
;
V
I
= GND or V
CC
; nOE = don’t care
74LVT162374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 4 — 1 October 2018
5 / 12
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