Si500D
D
IFFERENTIAL
O
UTPUT
S
I L I C O N
O
SCILLATOR
Features
Quartz-free, MEMS-free, and PLL-free all-silicon
oscillator
Any output frequencies from 0.9 to 200 MHz
Short lead times
Excellent temperature stability (±20 ppm)
Highly reliable startup and operation
High immunity to shock and vibration
Low jitter: <1.5 ps rms
0 to 85 °C operation includes 10-year aging in hot
environments
Footprint compatible with industry-
standard 3.2 x 5.0 mm XOs
CMOS, SSTL, LVPECL, LVDS, and HCSL
versions available
Driver stopped, tri-state, or powerdown
operation
RoHS compliant
1.8, 2.5, or 3.3 V options
Low power
More than 10x better fit rate than
competing crystal solutions
Specifications
Parameters
Frequency Range
Temperature stability,
0 to +70 °C
Temperature stability,
0 to +85 °C
Total stability,
0 to +70 °C operation
1
Total stability,
0 to +85 °C operation
2
Commercial
Extended commercial
1.8 V option
2.5 V option
3.3 V option
Condition
Min
0.9
—
—
—
—
0
0
–55
1.71
2.25
2.97
Typ
—
±10
±20
—
—
—
—
—
—
—
—
Max
200
—
—
±150
±250
70
85
+125
1.98
2.75
3.63
Units
MHz
ppm
ppm
ppm
ppm
°C
°C
°C
V
V
V
Frequency Stability
Operating Temperature
Storage Temperature
Supply Voltage
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3.
See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4.
V
TT
= .5 x V
DD
.
5.
V
TT
= .45 x V
DD
.
Rev. 1.1 10/11
Copyright © 2011 by Silicon Laboratories
Si500D
Si500D
Parameters
Condition
LVPECL
Low Power LVPECL
LVDS
HCSL
Differential CMOS(3.3 V option,
10 pF on each output, 200 MHz)
Differential CMOS(3.3 V option,
1 pFon each output, 40 MHz)
Differential SSTL-3.3
Differential SSTL-2.5
Differential SSTL-1.8
Tri-State
Powerdown
V
DIFF
= 0
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
From time V
DD
crosses min spec
supply
Min
—
—
—
—
—
—
—
—
—
—
—
46 – 13 ns/T
CLK
—
—
—
V
DD
– 1.5
.720
—
.68
1.15
0.25
0.85
0.25
0.35
0.65
45
V
DD
– 0.6
—
V
TT
+ 0.375
—
V
TT
+ 0.48
—
V
TT
+ 0.48
—
—
—
—
—
Typ
34.0
19.3
14.9
25.3
33
16
24.5
24.3
22.2
9.7
1.0
—
—
—
1.1
—
—
N/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
36.0
22.2
16.5
29.3
36
—
27.7
26.7
25
10.7
1.9
54 + 13 ns/T
CLK
460
800
1.6
V
DD
– 1.34
.880
—
.95
1.26
0.45
0.96
0.45
0.425
0.82
55
—
0.6
—
V
TT
– 0.375
—
V
TT
– 0.48
—
V
TT
– 0.48
2
250 + 3 x T
CLK
250 + 3 x T
CLK
12 + 3 x T
CLK
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ps
ps
ns
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
V
V
V
ms
ns
ns
µs
Supply Current
Output Symmetry
Rise and Fall Times (20/80%)
3
LVPECL Output Option
(DC coupling, 50
to V
DD
– 2.0 V)
3
Low Power LVPECL Output Option
(AC coupling, 100
Differential
Load)
3
LVDS Output Option (2.5/3.3 V)
(R
TERM
= 100
diff)
3
LVDS Output Option (1.8 V)
(R
TERM
= 100
diff)
3
HCSL Output Option
3
CMOS Output Voltage
3
SSTL-1.8 Output Voltage
4
SSTL-2.5 Output Voltage
4
SSTL-3.3 Output Voltage
5
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped
Mode
Return From Tri-State Time
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3.
See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4.
V
TT
= .5 x V
DD
.
5.
V
TT
= .45 x V
DD
.
2
Rev. 1.1
Si500D
Parameters
Return From Powerdown Time
Non-CMOS
Period Jitter (1-sigma)
CMOS, C
L
= 7 pF
1.0 MHz – min(20 MHz,
0.4 x F
OUT
),non-CMOS
1.0 MHz – min(20 MHz,
0.4 x F
OUT
),CMOS format
—
—
—
1
0.6
0.7
3
1
1.5
Condition
Min
—
—
Typ
—
1
Max
2
2
Units
ms
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Integrated Phase Jitter
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3.
See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4.
V
TT
= .5 x V
DD
.
5.
V
TT
= .45 x V
DD
.
Rev. 1.1
3
Si500D
Package Specifications
Table 1. Package Diagram Dimensions (mm)
Dimension
A
A1
b
D
e
E
L
Min
0.80
0.00
0.59
3.20 BSC.
1.27 BSC.
4.00 BSC.
0.95
1.00
1.05
Nom
0.85
0.03
0.64
Max
0.90
0.05
0.69
Dimension
L1
aaa
bbb
ccc
ddd
eee
Min
0.00
—
—
—
—
—
Nom
0.05
—
—
—
—
—
Max
0.10
0.10
0.10
0.08
0.10
0.05
Table 2. Pad Connections
1
2
3
4
5
6
OE
NC—Make no external
connection to this pin
GND
Output
Complementary Output
VDD
Table 3. Tri-State/Powerdown/Driver Stopped
Function on OE (3rd Option Code)
A
B
C
D
Active
Power-
down
E
Active
Active
F
Active
Driver
Stopped
Active
Open
Active Active Active
1
Tri-
Active
State
Level
Active
0
Tri-
Power-
Driver
Active
Active
down
Stopped
Level
State
Dimension
C1
E
X1
Y1
(mm)
2.70
1.27
0.75
1.55
0 C CC CC
T TTT TT
Y Y WW
0 = Si500
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 1. Recommended Land Pattern
Figure 2. Top Mark
4
Rev. 1.1
Si500D
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Solderability
Damp Heat
Moisture Sensitivity Level
Conditions/Test Method
MIL-STD-883, Method 2002.4
MIL-STD-883, Method 2007.3 A
MIL-STD-202, 260 C
°
for 8 seconds
MIL-STD-883, Method 2003.8
IEC 68-2-3
J-STD-020, MSL 3
Ordering Information
The Si500D supports a variety of options including frequency, output format, supply voltage, and tri-
state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.
Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can
be used to simplify part number configuration. Refer to
www.silabs.com/SiliconXOPartnumber
to access this tool.
The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel
packaging is available as an ordering option.
500D
Si500
Differential
Oscillator
X
X
X
XXMXXXX
Frequency
xMxxxxx: f
OUT
< 10 MHz
xxMxxxx: 10 MHz < f
OUT
< 100 MHz
xxxMxxx: f
OUT
> 100 MHz
3
rd
Option Code
Tri-State/Powerdown/
Output Driver Stopped
A
OE active high/tristate
B
OE active low/tristate
C
OE active high/powerdown
D
OE active low/powerdown
E
OE active high/driver stopped
F
OE active low/driver stopped
2
nd
Option Code
A
B
Stability (ppm, max)
±150
±250
A
C
X
R
R = Tape & Reel
Blank = Cut-Tape
1
st
Option Code
V
DD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
Format
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
Oper. Temp Range
F
0 to 70 °C
*H
0 to 85 °C
Product Revision = C
Package
A
3.2 x 4.0 mm SMD
*Note: Only +250 ppm is supported.
Rev. 1.1
5
FPGA/CPLD
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