4 Mbit (x8) Small-Sector Flash
SST29SF040 / SST29VF040
SST29SF/VF0404Mb (x8) Byte-Program, Small-Sector flash memories
Data Sheet
FEATURES:
• Organized as 512K x8
• Single Voltage Read and Write Operations
– 4.5-5.5V-only for SST29SF040
– 2.7-3.6V for SST29VF040
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 10 mA (typical)
– Standby Current:
30 µA (typical) for SST29SF040
1 µA (typical) for SST29VF040
• Sector-Erase Capability
– Uniform 128 Byte sectors
• Fast Read Access Time:
– 55 ns for SST29SF040
– 55 ns and 70 ns for SST29VF040
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility for SST29SF040
• CMOS I/O Compatibility for SST29VF040
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST29SF040 and SST29VF040 are 512K x8 CMOS
Small-Sector Flash (SSF) manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST29SF040 devices write
(Program or Erase) with a 4.5-5.5V power supply. The
SST29VF040 devices write (Program or Erase) with a 2.7-
3.6V power supply. These devices conform to JEDEC
standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST29SF040 and SST29VF040 devices provide a maxi-
mum Byte-Program time of 20 µsec. To protect against
inadvertent write, they have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of at
least 10,000 cycles. Data retention is rated at greater than
100 years.
The SST29SF040 and SST29VF040 devices are suited
for applications that require convenient and economical
updating of program, configuration, or data memory. For
all system applications, they significantly improve perfor-
mance and reliability, while lowering power consumption.
They inherently use less energy during Erase and Pro-
gram than alternative flash technologies. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
©2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
1
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. They also improve flexibility while low-
ering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high density, surface mount requirements, the
SST29SF040 and SST29VF040 devices are offered in 32-
lead PLCC and 32-lead TSOP packages. See Figures 1
and 2 for pin assignments.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit Small-Sector Flash
SST29SF040 / SST29VF040
Data Sheet
Read
The Read operation of the SST29SF040 and
SST29VF040 devices are controlled by CE# and OE#,
both have to be low for the system to obtain data from the
outputs. CE# is used for device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST29SF040 and SST29VF040 devices provide a
Chip-Erase operation, which allows the user to erase the
entire memory array to the “1s” state. This is useful when
the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 9 for timing diagram, and Figure 18 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Byte-Program Operation
The SST29SF040 and SST29VF040 devices are pro-
grammed on a byte-by-byte basis. Before programming,
the sector where the byte exists must be fully erased. The
Program operation is accomplished in three steps. The first
step is the three-byte load sequence for Software Data Pro-
tection. The second step is to load byte address and byte
data. During the Byte-Program operation, the addresses
are latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the rising
edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 4 and 5 for WE#
and CE# controlled Program operation timing diagrams
and Figure 15 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Write Operation Status Detection
The SST29SF040 and SST29VF040 devices provide
two software means to detect the completion of a Write
(Program or Erase) cycle, in order to optimize the system
Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE# which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The SST29SF040 and
SST29VF040 offer Sector-Erase mode. The sector archi-
tecture is based on uniform sector size of 128 Bytes. The
Sector-Erase operation is initiated by executing a six-byte-
command sequence with Sector-Erase command (20H)
and sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (20H) is latched on the rising
edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle
Bit methods. See Figure 8 for timing waveforms. Any com-
mands issued during the Sector-Erase operation are
ignored.
©2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
2
4 Mbit Small-Sector Flash
SST29SF040 / SST29VF040
Data Sheet
Data# Polling (DQ
7
)
When the SST29SF040 and SST29VF040 devices are
in the internal Program operation, any attempt to read
DQ
7
will produce the complement of the true data. Once
the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid
data immediately following the completion of an internal
Write operation, the remaining data outputs may still be
invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1
µs. During internal Erase operation, any attempt to read
DQ
7
will produce a ‘0’. Once the internal Erase operation
is completed, DQ
7
will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 6 for Data# Polling timing dia-
gram and Figure 16 for a flowchart.
Software Data Protection (SDP)
The SST29SF040 and SST29VF040 provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of a series of three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of a six-byte load sequence. These devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within T
RC.
Product Identification
The Product Identification mode identifies the devices as
SST29SF040 or SST29VF040 and manufacturer as SST.
This mode may be accessed by software operations. Users
may use the Software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 10 for the Software ID
Entry and Read timing diagram and Figure 17 for the Soft-
ware ID Entry command sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST29SF040
SST29VF040
0000H
0001H
0001H
Data
BFH
13H
14H
T1.2 1160
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing dia-
gram and Figure 16 for a flowchart.
Data Protection
The SST29SF040 and SST29VF040 devices provide both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 11 for timing wave-
form, and Figure 17 for a flowchart.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V for SST29SF040. The
Write operation is inhibited when V
DD
is less than 1.5V. for
SST29VF040.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
3
4 Mbit Small-Sector Flash
SST29SF040 / SST29VF040
Data Sheet
F
UNCTIONAL
B
LOCK
D
IAGRAM
X-Decoder
SuperFlash
Memory
Memory
Address
Address Buffers & Latches
Y-Decoder
CE#
OE#
WE#
DQ7 - DQ0
1160 B1.0
Control Logic
I/O Buffers and Data Latches
WE#
VDD
A12
A15
A16
A18
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32 31 30
29
28
27
26
25
24
23
22
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
32-lead PLCC
Top View
21
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
1160 32-plcc P01.0
FIGURE 1: P
IN
A
SSIGNMENTS FOR
32-
LEAD
PLCC
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1160 32-tsop P02.0
FIGURE 2: P
IN
A
SSIGNMENTS FOR
32-
LEAD
TSOP (8
MM
©2004 Silicon Storage Technology, Inc.
X
14
MM
)
S71160-10-000
2/04
4
4 Mbit Small-Sector Flash
SST29SF040 / SST29VF040
Data Sheet
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
Pin Name
Address Inputs
Data Input/output
Functions
To provide memory addresses. During Sector-Erase A
MS
-A
8
address lines will select the
sector.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
4.5-5.5V for SST29SF040
2.7-3.6V for SST29VF040
CE#
OE#
WE#
V
DD
V
SS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Pin not connected internally
T2.4 1160
1. A
MS
= Most significant address
A
MS
= A
18
for SST29SF/VF040
TABLE 3: O
PERATION
M
ODES
S
ELECTION
Mode
Read
Program
Erase
Standby
Write Inhibit
Product Identification
Software Mode
V
IL
V
IL
V
IH
See Table 4
T3.4 1160
CE#
V
IL
V
IL
V
IL
V
IH
X
X
OE#
V
IL
V
IH
V
IH
X
V
IL
X
WE#
V
IH
V
IL
V
IL
X
X
V
IH
DQ
D
OUT
D
IN
X
1
High Z
High Z/ D
OUT
High Z/ D
OUT
Address
A
IN
A
IN
Sector address,
XXH for Chip-Erase
X
X
X
1. X can be V
IL
or V
IH
, but no other value.
©2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
5
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