EMDS12D2J-187.5103M TR
Series
RoHS Compliant (Pb-free) 2.5V 6 Pad 5mm x 7mm
Plastic SMD LVDS MEMS Oscillator
Frequency Tolerance/Stability
±50ppm Maximum over 0°C to +70°C
Duty Cycle
50 ±5(%)
RoHS
Pb
Packaging Options
Tape & Reel
EMDS12 D 2 J -187.5103M TR
Nominal Frequency
187.5103MHz
Logic Control / Additional Output
Standby (ST) and Complementary Output
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
187.5103MHz
±50ppm Maximum over 0°C to +70°C (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency
Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year
Aging at 25°C, Reflow, Shock, and Vibration)
±1ppm First Year Maximum
+2.5Vdc ±0.125Vdc
75mA Maximum (Excluding Load Termination Current)
1.425Vdc Typical
1.075Vdc Typical
247mVdc Minimum, 350mVdc Typical, 454mVdc Maximum
1.125V Minimum, 1.250V Typical, 1.375V Maximum
225pSec Typical, 325pSec Maximum (Measured over 20% to 80% of waveform)
50mVdc Maximum
50 ±5(%) (Measured at 50% of waveform)
50mVdc Maximum
100 Ohms Between Output and Complementary Output
LVDS
Standby (ST) and Complementary Output
Vih of 70% of Vcc Minimum or No Connect to Enable Output and Complementary Output, Vil of 30% of Vcc
Maximum to Disable Output and Complementary Output (High Impedance)
30µA Maximum (ST) Without Load
0.2pSec Typical
2.0pSec Typical
2.5pSec Typical, 3.5pSec Maximum
25pSec Typical, 30pSec Maximum
1.6pSec Typical
0.7pSec Typical
0.6pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Differential Output Voltage (Vod)
Offset Voltage (Vos)
Rise/Fall Time
Differential Output Error (dVod)
Duty Cycle
Offset Error (dVos)
Load Drive Capability
Output Logic Type
Logic Control / Additional Output
Output Control Input Voltage
Standby Current
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
RMS Phase Jitter (Fj = 637kHz to
10MHz; Random)
RMS Phase Jitter (Fj = 1MHz to
20MHz; Random)
RMS Phase Jitter (Fj = 1.875MHz to
20MHz; Random)
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Flammability
Mechanical Shock
Moisture Resistance
Moisture Sensitivity Level
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
MIL-STD-883, Method 3015, Class 2, HBM 2000V
UL94-V0
MIL-STD-883, Method 2002, Condition G, 30,000G
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003 (Six I/O Pads on bottom of package only)
MIL-STD-883, Method 1010, Condition B
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 1 of 6
EMDS12D2J-187.5103M TR
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Thermal Shock
Vibration
MIL-STD-883, Method 1011, Condition B
MIL-STD-883, Method 2007, Condition A, 20G
MECHANICAL DIMENSIONS (all dimensions in millimeters)
5.00
±0.15
0.85
±0.15
0.08
MAX
3
7.00
±0.15
5.08
±0.10
4
PIN
CONNECTION
Standby (ST)
No Connect
Case Ground
Output
Complementary Output
Supply Voltage
1.20 ±0.10 (x4)
1.47
1
2
3
4
5
6
2
A
5
2.30
LINE MARKING
1
1
2.54 TYP
2.60
±0.15
6
1.40
±0.10 (x4)
XXXX or XXXXX
XXXX or XXXXX=Ecliptek
Manufacturing Lot Code
Note A: Center paddle is connected
internally to oscillator ground (Pad 3).
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.80 (X6)
2.00 (X6)
0.54 (X4)
2.39 (X3)
All Tolerances are ±0.1
Solder Land
(X6)
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 2 of 6
EMDS12D2J-187.5103M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
Q & Q OUTPUTS
V
OH
V
OS
V
OL
V
OD
Q
HIGH IMPEDANCE
STATE
Q
Q MINUS Q OUTPUT
80%
0V
V
Op-p
HIGH IMPEDANCE
STATE
20%
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for Tri-State and Complementary Output
Oscilloscope
Frequency
Counter
Current
Meter
0.01µF
(Note 1)
Supply
Voltage
(V
DD
)
Probe 2
(Note 2)
Probe 1
(Note 2)
100 Ohms
Complementary
Output
Output
Switch
0.1µF
(Note 1)
Ground
Power
Supply
Voltage
Meter
Power
Supply
Tri-State
No
Connect
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass capacitor close (less than 2mm)
to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>500MHz) passive probe is
recommended.
Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 3 of 6
FPGA/CPLD
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