Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
SST32HF64A1 / 64B164Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
(x16) MCP ComboMemories
Preliminary Specifications
FEATURES:
• ComboMemories organized as:
– SST32HF64A2: 4M x16 Flash + 1024K x16 PSRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to PSRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or PSRAM Read
– Standby Current: 60 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Times:
– Flash: 70 ns
– PSRAM: 70 ns
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST32HF64A2
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Flash Automatic Erase and Program Timing
– Internal V
PP
Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 56-ball LFBGA (8mm x 10mm x 1.4mm)
– 64-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF64A2 ComboMemory device integrates a
CMOS flash memory bank with a CMOS PseudoSRAM
(PSRAM) memory bank in a Multi-Chip Package (MCP),
manufactured with SST proprietary, high-performance
SuperFlash technology.
Featuring high-performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF64A2 device contains on-chip hardware and soft-
ware data protection schemes. The SST32HF64A2 device
offers a guaranteed endurance of 10,000 cycles, and data
retention greater than 100 years.
The SST32HF64A2 device consists of two independent
memory banks, each with enable signals. The flash and
PSRAM memory banks are superimposed in the same
memory address space, and both banks share common
address lines, data lines, WE# and OE#. The memory
bank is selected using the memory bank enable signals.
The PSRAM bank enable signal, BES1#, selects the
PSRAM bank. The flash memory bank enable signal,
©2006 Silicon Storage Technology, Inc.
S71299-02-000
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BEF#, selects the flash memory bank. The WE# signal is
used with the Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF64A2 provides the added functionality of
being able to simultaneously read from, or write to, the
PSRAM bank while erasing or programming in the flash
memory bank. The PSRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
required. Once the internally controlled Erase or Program
cycle in the flash bank commences, the PSRAM bank can
be accessed for Read or Write.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
Preliminary Specifications
The SST32HF64A2 device is suited for applications that
use both flash memory and PSRAM memory to store code
or data, and is ideal for systems requiring low power and
small form factor. The SST32HF64A2 significantly
improves performance and reliability, while lowering power
consumption, when compared with multiple chip solutions.
The total energy consumed is a function of the applied volt-
age, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Concurrent Read/Write State Table
Flash
Program/Erase
Program/Erase
PSRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST32HF64A2 is controlled by
BEF# and OE#. Both have to be low, with WE# high, for
the system to obtain data from the outputs. BEF# is used
for flash memory bank selection. When BEF# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to Figure 7 for further details.
Device Operation
The SST32HF64A2 uses BES1#, BES2 and BEF# to con-
trol operation of either the flash or the PSRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low
and BES2 is high, the PSRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time.
If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
PSRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high and BES2 is low.
Flash Word-Program Operation
The flash memory bank of the SST32HF64A2 is pro-
grammed on a word-by-word basis. Before Program opera-
tions, the memory must be erased first. The Program
operation consists of three steps.
1. Load the three-byte sequence for Software Data
Protection.
2. Load word address and word data. During the
Word-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or BEF#, whichever
occurs first. The Program operation, once initi-
ated, will be completed, within 10 µs. See Figures
8 and 9 for WE# and BEF# controlled Program
operation timing diagrams, and Figure 23 for flow-
charts.
During the Program operation, the only valid flash Read
operations are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. During the command sequence, WP# should
be statically held high or low. Any SDP commands loaded
during the internal Program operation will be ignored.
Concurrent Read/Write Operation
The SST32HF64A2 provides the unique benefit of being
able to read from or write to PSRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from PSRAM, while altering the
data in flash. See Figure 28 for a flowchart. The following
table lists all valid states.
©2006 Silicon Storage Technology, Inc.
S71299-02-000
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Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
Preliminary Specifications
Flash Sector/Block-Erase Operation
The SST32HF64A2 offers both Sector-Erase and Block-
Erase operations. The Flash Sector/Block-Erase operation
erases the device on a sector-by-sector (or block-by-block)
basis. The sector architecture is based on uniform sector
size of 2 KWord. The Block-Erase mode is based on uni-
form block size of 32 KWord.
Initiate the Sector-Erase operation by executing a six-byte
command sequence with Sector-Erase command (50H)
and sector address (SA) in the last bus cycle. The address
lines A
MS
-A
11
are used to determine the sector address.
Initiate the Block-Erase operation by executing a six-byte
command sequence with Block-Erase command (30H)
and block address (BA) in the last bus cycle. The address
lines A
MS
-A
15
are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse.
Erase operations begin after the sixth WE# pulse. The
End-of-Erase operation can be determined using either
Data# Polling or Toggle Bit methods. See Figures 13 and
14 for timing waveforms. Any commands issued during the
Sector- or Block-Erase operation are ignored, WP# should
be statically held high or low.
Flash Chip-Erase Operation
The SST32HF64A2 provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the ‘1’ state. This is useful when the entire device must be
quickly erased.
Initiate the Chip-Erase operation executing a six- byte
command sequence with Chip-Erase command (10H) at
address 555H in the last byte sequence. The Erase opera-
tion begins with the rising edge of the sixth WE# or BEF#,
whichever occurs first. During the Erase operation, the
only valid read is Toggle Bit or Data# Polling. See Table 6
for the command sequence, Figure 11 for timing diagram,
and Figure 27 for the flowchart. Any commands issued
during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF64A2 provides two software means to detect
the completion of a write (Program or Erase) cycle, in order
to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may get an
erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6.
To prevent spurious rejection, in the
event of an erroneous result, the software routine must
include a loop to read the accessed location an additional
two (2) times. If both reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation allowing data to be read
from any memory location, or programed to any sector/
block that is not suspended for an Erase operation. Exe-
cute the operation by issuing a one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
2
toggling and DQ
6
at ‘1’. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume the Sector-Erase or Block-Erase operation which
has been suspended, the system must issue the Erase
Resume command. Execute the operation by issuing a one
byte command sequence with Erase-Resume command
(30H) at any address in the last Byte sequence.
©2006 Silicon Storage Technology, Inc.
S71299-02-000
11/06
3
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
Preliminary Specifications
Flash Data# Polling (DQ
7
)
When the SST32HF64A2 flash memory banks are in the
internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Pro-
gram operation is complete, DQ
7
will produce true data.
However, even though DQ
7
may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid. Valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 µs.
During internal Erase operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase operation is
complete, DQ
7
will produce a ‘1’. The Data# Polling is valid
after the rising edge of the fourth WE# (or BEF#) pulse for
Program operation. For Sector- or Block-Erase, the Data#
Polling is valid after the rising edge of the sixth WE# (or
BEF#) pulse. See Figure 10 for Data# Polling timing dia-
gram and Figure 24 for a flowchart.
TABLE 1: Write Operation Status
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Program
DQ
7
DQ
7
#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
Data
Data
Data
DQ
7
#
Toggle
N/A
T1.0 1299
Note:
DQ
7
and DQ
2
require a valid address when reading
status information.
Flash Memory Data Protection
The SST32HF64A2 flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
bit will alternate between ‘1’
and ‘0’. When the internal Program or Erase operation is
complete, the DQ
6
bit will stop toggling. The device is then
ready for the next operation.
For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
6
) is
valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ
6
will be set to ‘1’ if a Read operation is attempted on an
Erase-Suspended Sector/Block. If a Program operation is
initiated in a sector/block not selected in Erase-Suspend
mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which is used
in conjunction with DQ
6
to check whether a particular sec-
tor is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
2
) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 11 for Toggle
Bit timing diagram and Figure 24 for a flowchart.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
©2006 Silicon Storage Technology, Inc.
S71299-02-000
11/06
4
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
Preliminary Specifications
Hardware Block Protection
The SST32HF64A2 supports top hardware block protec-
tion, which protects the top 32 KWord block of the device.
The Boot Block address ranges are described in Table 2.
Program and Erase operations are prevented on the 32
KWord when WP# is low. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
TABLE 2: Boot Block Address Ranges
Product
Top Boot Block
SST32HF64A2
3F8000H-3FFFFFH
T2.0 1299
PSRAM Deep Power-down Mode
The PSRAM Deep Power-down Mode is used to lower the
power consumption of the PSRAM in the SST32HF64A2.
Deep Power-down occurs 1 µs after being enabled by driv-
ing BES2 low. Normal operation occurs 500 µs after driving
BES2 high. In Deep Power-down mode, PSRAM data is
lost. See Figure 22 for the state diagram.
PSRAM Read
The PSRAM Read operation of the SST32HF64A2 is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when OE# is high. Refer to the Read cycle timing dia-
gram, Figure 4, for further details.
Address Range
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
RHR
is
required after RST# is driven high before a valid Read can
take place (see Figure 18).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
PSRAM Write
The PSRAM Write operation of the SST32HF64A2 is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the PSRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1# or WE#, which-
ever occurs first. The write time is measured from the last
falling edge of BES1# or WE# to the first rising edge of
BES1# or WE#. Refer to the Write cycle timing diagrams,
Figures 5 and 6, for further details.
Flash Software Data Protection (SDP)
The SST32HF64A2 provides the JEDEC approved soft-
ware data protection scheme for all flash memory bank
data-alteration operations, i.e., Program and Erase. Any
Program operation requires a three-byte sequence series.
Using the three byte-load sequence to initiate the Program
operation, provides optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires a six-byte load
sequence.
The SST32HF64A2 devices are shipped with the software
data protection permanently enabled. See Table 6 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or
V
IH,
but no other value, during any SDP command
sequence.
©2006 Silicon Storage Technology, Inc.
S71299-02-000
11/06
5
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