16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
FEATURES:
•
Organized as 1M x16
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit Bottom Sector Protection
- SST36VF1601: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602: 4 Mbit + 12 Mbit
• Single 2.7-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
•
Hardware Sector Protection/WP# Input Pin
– Protects 4 outer most sectors (4 KWord) in the
larger bank by driving WP# low and unprotects
by driving WP# high
•
Hardware Reset Pin (RESET#)
– Resets the internal state machine to reading
data array
•
Sector-Erase Capability
– Uniform 1 KWord sectors
•
Block-Erase Capability
– Uniform 32 KWord blocks
PRODUCT DESCRIPTION
The SST36VF1601/1602 are 1M x16 CMOS Concurrent
Read/Write Flash Memory manufactured with SST’s pro-
prietary, high performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches.The SST36VF1601/
1602 write (Program or Erase) with a 2.7-3.6V power
supply. The SST36VF1601/1602 devices conform to
JEDEC standard pinouts for x16 memories.
Featuring high performance Word-Program, the
SST36VF1601/1602 devices provide a typical Word-Pro-
gram time of 14 µsec. The devices use Toggle Bit or Data#
Polling to detect the completion of the Program or Erase
operation. To protect against inadvertent write, the
SST36VF1601/1602 devices have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, the
SST36VF1601/1602 devices are offered with a guaran-
teed endurance of 10,000 cycles. Data retention is rated
at greater than 100 years.
•
Read Access Time
– 70 and 90 ns
•
Latched Address and Data
•
Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
•
Automatic Write Timing
– Internal V
PP
Generation
•
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
•
CMOS I/O Compatibility
•
Conforms to Common Flash Memory
Interface (CFI)
•
JEDEC Standards
– Flash EEPROM Pinouts and command sets
•
Packages Available
– 48-Pin TSOP (12mm x 20mm)
– 48-Ball TFBGA (8mm x 10mm)
1
2
3
4
5
6
7
8
9
10
The SST36VF1601/1602 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applica-
tions, the SST36VF1601/1602 significantly improve per-
formance and reliability, while lowering power consump-
tion. The SST36VF1601/1602 inherently use less energy
during Erase and Program than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program
operation is less than alternative flash technologies. The
SST36VF1601/1602 also improve flexibility while lower-
ing the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified or
de-rated as is necessary with alternative flash technolo-
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Concurrent SuperFlash is a trademark of Silicon Storage Technology, Inc.
373-3 11/00
S71142
These specifications are subject to change without notice.
1
16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
gies, whose Erase and Program times increase with
accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST36VF1601/1602 are offered in 48-pin TSOP and 48-
ball TFBGA packages. See Figures 3 and 4 for pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while keeping
CE# low. The address bus is latched on the falling edge
of WE# or CE#, whichever occurs last. The data bus is
latched on the rising edge of WE# or CE#, whichever
occurs first.
The SST36VF1601/1602 also have the
Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the I
DD
active read current to typically 4 µA. The
device exits the Auto Low Power mode with any address
transition or control signal transition used to initiate
another read cycle, with no access time penalty.
Concurrent Read/Write Operation
Dual bank architecture of SST36VF1601/1602 devices
allows the Concurrent Read/Write operation whereby the
user can read from one bank while program or erase in the
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 5).
Word-Program Operation
The SST36VF1601/1602 are programmed on a word-by-
word basis. The Program operation consists of three steps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever occurs first.
The third step is the internal Program operation which is
initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed within 10 µs. See Figures 6 and 7 for
WE# and CE# controlled Program operation timing dia-
grams and Figure 19 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Toggle
Bit. During the internal Program operation, the host is free
to perform additional tasks. Any commands issued during
the internal Program operation are ignored.
Sector- (Block-) Erase Operation
The Sector- (Block-) Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF1601/1602 offer both Sector-Erase
and Block-Erase mode. The sector architecture is based on
uniform sector size of 1 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-Erase
operation is initiated by executing a six-byte command
sequence with Sector-Erase command (30H) and sector
address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. See Figures 11
and 12 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST36VF1601/1602 provide a Chip-Erase operation,
which allows the user to erase all unprotected sectors/
blocks to the “1” state. This is useful when the device must
be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
2
S71142
373-3 11/00
Note: For the purposes of this table, write means to Block-,
Sector-, or Chip-Erase, or Word-Program as applicable to
the appropriate bank.
Read
The Read operation of the SST36VF1601/1602 is con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is
© 2000 Silicon Storage Technology, Inc.
16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
CE#, whichever occurs first. During the Erase operation, the
only valid read is Toggle Bits or Data# Polling. See Table 4
for the command sequence, Figure 10 for timing diagram,
and Figure 22 for the flowchart. Any commands issued
during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST36VF1601/1602 provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system write
cycle time. The hadware detection uses the Ready/Busy#
(RY/BY#) output pin. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
End-of-Write detection mode is enabled after the rising edge
of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ
7
) or Toggle Bit (DQ
6
) read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may possibly get an erroneous
result, i.e., valid data may appear to conflict with either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an errone-
ous result occurs, the software routine should include a loop
to read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The SST36VF1601/1602 includes a Ready/Busy# (RY/
BY#) output signal. During any SDP initiated operation, e.g.,
Erase, Program, CFI or ID Read operation, RY/BY# is
actively pulled low, indicating a SDP controlled operation is
in Progress. The status of RY/BY# is valid after the rising
edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-, Block- or Bank-Erase, the RY/BY# is valid after
the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an
open drain output that allows several devices to be tied in
parallel to V
DD
via an external pull up resistor. Ready/Busy#
is in high impedance whenever OE# or CE# is high or RST#
is low.
Data# Polling (DQ
7
)
When the SST36VF1601/1602 are in the internal Program
operation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ
7
will produce true data. The device is then
ready for the next operation. During internal Erase operation,
any attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling (DQ
7)
is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling (DQ
7)
is valid after
© 2000 Silicon Storage Technology, Inc.
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Data# Polling (DQ
7)
timing diagram and Figure 20 for a
flowchart.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next
operation. The Toggle Bit (DQ
6
) is valid after the rising edge
of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Toggle Bit (DQ
6
) is valid
after the rising edge of sixth WE# (or CE#) pulse. See Figure
9 for Toggle Bit timing diagram and Figure 21 for a flowchart.
Data Protection
The SST36VF1601/1602 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
Hardware Block Protection
The SST36VF1601/1602 provide a hardware block protec-
tion which protects the outermost 4 KWords in the larger
bank.The block is protected when WP# is held low. See
Figures 1 and 2 for Block-Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire write
operation has completed.
Hardware Reset (RESET#)
When the RESET# input pin is held low for at least T
RP
, any
in progress operation will terminate and return to Read
mode. If the part is not busy, a minimum period of T
RHR
is
required after RESET# is driven high before a valid read can
take place. If the part is busy, poll RY/BY#, Data# Polling,
or Toggle Bit to determine when the device is ready.
Initiating a reset during a Write operation (Program or
Erase) is not recommended. Data may be in an undeter-
mined state.
S71142
373-3 11/00
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3
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12
13
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15
16
3
16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
Software Data Protection (SDP)
The SST36VF1601/1602 provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence.
The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires
the inclusion of six-byte sequence. The SST36VF1601/
1602 are shipped with the Software Data Protection
permanently enabled. See Table 4 for the specific soft-
ware command codes. During SDP command sequence,
invalid commands will abort the device to Read mode
within T
RC
. The contents of DQ
15
-DQ
8
are “Don’t Care”
during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST36VF1601/1602 also contain the CFI informa-
tion to describe the characteristics of the device. In order
to enter the CFI Query mode, the system must write
three-byte sequence, same as Software ID Entry com-
mand with 98H (CFI Query command) to address 555H
in the last byte sequence. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 5 through 7. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices
and manufacturer. For details, see Table 4 for software
operation, Figure 13 for the Software ID Entry and Read
timing diagram and Figure 21 for the Software ID Entry
command sequence flowchart.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
WORD
Manufacturers ID
Device ID SST36VF1601
Device ID SST36VF1602
0000 H
0001 H
0001 H
DATA
00BF H
2761 H
2762 H
373 PGM T1.0
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the
Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit
command sequence, which returns the device to the
Read mode. This command may also be used to reset the
device to the Read mode after any inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g., not read correctly. Please note that the
Software ID Exit/CFI Exit command is ignored during an
internal Program or Erase operation. See Table 4 for
software command codes, Figure 15 for timing waveform
and Figure 21 for a flowchart.
F
UNCTIONAL
B
LOCK
D
IAGRAM
Memory
Address
Address
Buffers
(4 KWord Sector Protection)
SuperFlash Memory
12 Mbit Bank
RESET#
CE#
WP#
WE#
OE#
RY/BY#
373 ILL B37.4
SuperFlash Memory
4 Mbit Bank
Control
Logic
I/O Buffers
DQ15 - DQ0
© 2000 Silicon Storage Technology, Inc.
4
S71142
373-3 11/00
16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
00FFFFH
008000H
007FFFH
001000H
000FFFH
000000H
Block 31
Block 30
Block 29
1
2
Bank 2
Bank 1
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
3
4
5
6
7
8
9
10
11
12
13
14
15
373 ILL F38.2
4 KWord Sector Protection
(4- 1 KWord Sectors)
Block 0
16
F
IGURE
1: SST36VF1601, 1 M
EGABIT X
16 C
ONCURRENT
S
UPER
F
LASH
D
UAL
-B
ANK
M
EMORY
O
RGANIZATION
© 2000 Silicon Storage Technology, Inc.
5
S71142
373-3 11/00
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