512 Kbit (x8) Multi-Purpose Flash
SST39SF512
SST39SF5125.0V 512Kb (x8) MPF memory
Data Sheet
FEATURES:
• Organized as 64K x8
• Single 4.5-5.5V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 10 mA (typical)
– Standby Current: 10 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Byte-Program
– Sector-Erase Time: 7 ms (typical)
– Chip-Erase Time: 15 ms (typical)
– Byte-Program Time: 20 µs (typical)
– Chip Rewrite Time: 2 seconds (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF512 are CMOS Multi-Purpose Flash (MPF)
manufactured with SST’s proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39SF512 devices write (Program or Erase) with a
4.5-5.5V power supply. The SST39SF512 device conforms
to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF512 devices provide a maximum Byte-Program
time of 30 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent write, they have on-chip hard-
ware and Software Data Protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF512 devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF512 are offered in 32-lead PLCC, 32-lead TSOP
,
and a 600 mil, 32-pin PDIP packages. See Figures 1, 2,
and 3 for pin assignments.
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
internal Erase operation begins after the sixth WE# pulse.
The end of Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.
Chip-Erase Operation
The SST39SF512 provide Chip-Erase operation, which
allows the user to erase the entire memory array to the “1s”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 4 for the command sequence,
Figure 10 for timing diagram, and Figure 18 for the flow-
chart. Any commands written during the Chip-Erase opera-
tion will be ignored.
Read
The Read operation of the SST39SF512 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 4).
Byte-Program Operation
The SST39SF512 are programmed on a byte-by-byte
basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed, within 30 µs.
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 15 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation
will be ignored.
Write Operation Status Detection
The SST39SF512 provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
Program or Erase cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ
7
or DQ
6
. In order to prevent spuri-
ous rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed loca-
tion an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise
the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising edge of the sixth WE# pulse. The
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
2
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
Data# Polling (DQ
7
)
When the SST39SF512 are in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. Note that even thought DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program Operation. For sector or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.
Software Data Protection (SDP)
The SST39SF512 provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three byte sequence. The three-
byte load sequence is used to initiate the Program opera-
tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-
byte load sequence. The SST39SF512 device is shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode, within T
RC.
Product Identification
The Product Identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details,
Table 4 for software operation, Figure 11 for the software ID
entry and read timing diagram and Figure 17 for the ID
entry command sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST39SF512
0001H
B4H
T1.3 1149
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with “1”. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data
BFH
0000H
Data Protection
The SST39SF512 provide both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
3
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
F
UNCTIONAL
B
LOCK
D
IAGRAM
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffers & Latches
Y-Decoder
CE#
OE#
WE#
DQ7 - DQ0
1149 B1.1
Control Logic
I/O Buffers and Data Latches
WE#
VDD
A12
A15
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32 31 30
29
28
27
26
25
24
23
22
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
32-lead PLCC
Top View
21
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
1149 F02b.6
FIGURE 1: P
IN
A
SSIGNMENTS FOR
32-
LEAD
PLCC
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
4
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1149 F01.3
FIGURE 2: P
IN
A
SSIGNMENTS FOR
32-
LEAD
TSOP (8
MM
X
14
MM
)
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
32-pin
6
PDIP
7
8
Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1149 F02a.4
FIGURE 3: P
IN
A
SSIGNMENTS FOR
32-
PIN
PDIP
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
