TDA7492PE
45 W + 45 W dual BTL class-D audio amplifier
Datasheet - production data
•
•
•
•
•
•
•
•
Features
•
•
•
Wide-range single-supply operation
(7 - 26 V)
Possible output configurations:
−
2 x PBTL
−
1 x Parallel BTL
BTL output capabilities (V
CC
= 22 V):
−
−
−
−
−
−
HD 10%
Parallel BTL output capabilities (V
CC
= 22 V):
−
−
High efficiency
Four selectable, fixed-gain settings of
nominally 20.8 dB, 26.8 dB, 30 dB and
32.8 dB
Differential inputs minimize common-mode
noise
Standby, mute and play operating modes
Short-circuit protection
Output power limited by P
LIMIT
function
Detection of shorted output pins during
startup
Thermal overload protection
ECOPACK
®
environmentally friendly
package
Description
The TDA7492PE is a dual BTL class-D audio
amplifier with single power supply designed for
home audio applications.
The device is housed in a 36-pin PowerSSO
package with exposed pad down (EPD) to
facilitate power dissipation through a properly
designed PCB area underneath the TDA7492PE.
Table 1: Device summary
Order code
TDA7492PE
TDA7492PETR
-40 to +85°C
Operating
temp. range
Package
PowerSSO-36
EPD
Packaging
Tube
Tape and
reel
•
•
February 2017
DocID027029 Rev 2
1/23
www.st.com
This is information on a product in full production.
Contents
TDA7492PE
Contents
1
2
Device block diagram...................................................................... 5
Pin description ................................................................................ 6
2.1
2.2
Pinout................................................................................................ 6
Pin list ............................................................................................... 7
Absolute maximum ratings ................................................................ 8
Thermal data ..................................................................................... 8
Electrical specifications ..................................................................... 9
Stereo BTL application.................................................................... 10
Parallel BTL (mono) application ...................................................... 10
Gain setting ..................................................................................... 11
Stereo and mono applications......................................................... 11
Smart protections ............................................................................ 11
4.3.1
4.3.2
4.3.3
Overcurrent protection (OCP) .......................................................... 11
Thermal protection............................................................................ 12
Power limit ........................................................................................ 12
3
Electrical specifications.................................................................. 8
3.1
3.2
3.3
3.4
3.5
4
Application information ................................................................ 11
4.1
4.2
4.3
4.4
Mode selection ................................................................................ 13
5
6
7
8
Schematic diagram........................................................................ 15
Characterization curves ................................................................ 17
Package information ..................................................................... 19
7.1
PowerSSO36 EPD package information......................................... 19
Revision history ............................................................................ 22
2/23
DocID027029 Rev 2
TDA7492PE
List of tables
List of tables
Table 1: Device summary ...........................................................................................................................1
Table 2: Pin description list .........................................................................................................................7
Table 3: Absolute maximum ratings ...........................................................................................................8
Table 4: Thermal data.................................................................................................................................8
Table 5: Electrical specifications.................................................................................................................9
Table 6: Stereo BTL application ...............................................................................................................10
Table 7: Stereo BTL (mono) application ...................................................................................................10
Table 8: Gain settings ...............................................................................................................................11
Table 9: Overcurrent protection ................................................................................................................11
Table 10: Overcurrent protection (mute mode) ........................................................................................12
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load...............................................13
Table 12: Mode settings............................................................................................................................13
Table 13: BTL configuration......................................................................................................................16
Table 14: PowerSSO-36 EPD package mechanical data ........................................................................21
Table 15: Document revision history ........................................................................................................22
DocID027029 Rev 2
3/23
List of figures
TDA7492PE
List of figures
Figure 1: Internal block diagram (showing one channel only) ....................................................................5
Figure 2: Pin connections (top view, PCB view) .........................................................................................6
Figure 3: Mono BTL settings.....................................................................................................................11
Figure 4: Recommended power limit pin connections..............................................................................12
Figure 5: Standby and mute circuits .........................................................................................................14
Figure 6: Turn-on/off sequence for minimizing speaker “pop”..................................................................14
Figure 7: Application circuit.......................................................................................................................15
Figure 8: Output power vs. supply voltage ...............................................................................................17
Figure 9: Efficiency vs. output power........................................................................................................17
Figure 10: THD vs. output power (f = 1 kHz) ............................................................................................17
Figure 11: THD vs. output power (100 Hz) ...............................................................................................17
Figure 12: THD vs. frequency...................................................................................................................17
Figure 13: Frequency response................................................................................................................17
Figure 14: FFT (0 dB) ...............................................................................................................................18
Figure 15: FFT (-60 dB) ............................................................................................................................18
Figure 16: PSRR parameter .....................................................................................................................18
Figure 17: PowerSSO-36 EPD package outline.......................................................................................20
4/23
DocID027029 Rev 2
TDA7492PE
Device block
diagram
1
Device block diagram
Figure 1: "Internal block diagram (showing one channel only)"
shows the block diagram of
one of the two identical channels of the TDA7492PE.
Figure 1: Internal block diagram (showing one channel only)
GAIN
PLMT
Gain Settings
Power Limit
-
+
INP
INN
+
-
-
+
+
-
VREF
Gate
Driver
+
-
OUTP
+
-
PWM logic level shift
Gate
Driver
ROSC
Oscillator
SYNCLK
OUTN
Standby Mute/Play
Thermal,Undervoltage
Overcurrent protections
VDD,VSS Regulators
STANDBY
MUTE
DIAG
VDDS
VSS
DocID027029 Rev 2
5/23
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