EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
RT
16 15 14 13
UD PACKAGE
16-LEAD (3mm
×
3mm) PLASTIC QFN
θ
JA
= 68°C/W,
θ
JC
= 4.2°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3689EMSE#PBF
LT3689IMSE#PBF
LT3689HMSE#PBF
LT3689EMSE-5#PBF
LT3689IMSE-5#PBF
LT3689HMSE-5#PBF
LT3689EUD#PBF
LT3689IUD#PBF
LT3689EUD-5#PBF
LT3689IUD-5#PBF
TAPE AND REEL
LT3689EMSE#TRPBF
LT3689IMSE#TRPBF
LT3689HMSE#TRPBF
LT3689EMSE-5#TRPBF
LT3689IMSE-5#TRPBF
LT3689HMSE-5#TRPBF
LT3689EUD#TRPBF
LT3689IUD#TRPBF
LT3689EUD-5#TRPBF
LT3689IUD-5#TRPBF
PART MARKING*
3689
3689
3689
36895
36895
36895
LDND
LDND
LFFM
LFFM
PACKAGE DESCRIPTION
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead Plastic MSOP with Exposed Pad
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
3689fe
2
For more information
www.linear.com/LT3689
LT3689/LT3689-5
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
V
IN
Fixed Undervoltage Lockout
V
IN
Overvoltage Lockout
Quiescent Current from V
IN
Quiescent Current from OUT
V
EN/UVLO
= 0.3V
V
OUT
= 3V, Not Switching
V
OUT
= 0V, Not Switching
V
EN/UVLO
= 0.3V
V
OUT
= 3V, Not Switching (Note 7)
V
OUT
= 0V, Not Switching
V
EN/UVLO
= 0.3V
V
OUT
= 5.5V (Note 8)
V
OUT
= 0V
V
EN/UVLO
= 0.3V
V
OUT
= 5.5V
The
l
denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 12V, V
OUT
= 5V, unless otherwise noted. (Note 3)
CONDITIONS
l
l
l
MIN
36
TYP
3.4
38
0.01
50
125
0.01
75
–5
0.01
50
125
8
95
MAX
3.7
40
0.5
95
175
0.5
150
–20
0.5
95
175
16
150
0.812
0.812
5.050
5.100
–100
UNITS
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
nA
%/V
%/V
l
LT3689-5 Quiescent Current from V
IN
LT3689-5 Quiescent Current from OUT
LT3689 FB Voltage
l
l
l
0.790
0.780
4.950
4.900
0.800
5.000
–30
0.005
0.005
LT3689-5 Output Voltage
l
LT3689 FB Pin Bias Current
LT3689 FB Voltage Line Regulation
LT3689-5 Output Voltage Line Regulation
f
SW
t
SW(OFF)
Switching Frequency
Switch Off-Time
Foldback Frequency
Switch Current Limit (Note 4)
Switch V
CESAT
Switch Leakage Current
DA Current Limit
Boost Schottky Reverse Leakage
Minimum BST Above SW Voltage
BST Pin Current
EN/UVLO Threshold Voltage
EN/UVLO Pin Current
EN/UVLO Pin Current Hysteresis
SYNC Threshold Voltage
V
RST
t
RST
t
WDU
t
WDL
V
OL
V
OH
Reset Threshold as % of V
FB
Reset Timeout Period
Watchdog Upper Boundary
Watchdog Lower Boundary
RST, WDO
Output Voltage Low
RST, WDO
Output Voltage High (Note 6)
V
FB
= 0.800V
5V < V
IN
< 36V
5.5V < V
IN
< 36V
R
T
= 4.02k
R
T
= 31.62k
R
T
= 4.02k, V
FB
= 0V
l
l
l
1.8
420
2
500
120
250
2.2
540
160
1.95
1
1.5
5
2.5
25
1.350
1
5.5
4.8
1
92
21
21
785
0.4
0.3
MHz
kHz
ns
kHz
A
mV
µA
A
µA
V
mA
V
µA
µA
µA
V
%
ms
ms
µs
V
V
V
l
1.15
1.55
450
0.01
I
SW
= 0.8A
0.85
V
BST
= 12V, V
OUT
= 0V
I
SW
= 0.8A
1.150
V
EN/UVLO
= 1.35V
V
EN/UVLO
= 1.15V
I(V
EN/UVLO
= 1.15V) – I(V
EN/UVLO
= 1.35V)
l
1.2
0.1
1.8
15
1.260
0. 01
4.1
3.8
0.8
90
19
19
675
0.15
0.05
2.5
2.8
0.4
88
17
17
610
C
POR
= 8200pF
C
WDT
= 1000pF
C
WDT
= 1000pF
I
SINK
= 2.5mA
I
SINK
= 100µA
l
l
l
l
l
l
V
OUT
–1
3689fe
For more information
www.linear.com/LT3689
3
LT3689/LT3689-5
ELECTRICAL CHARACTERISTICS
SYMBOL
t
UV
PARAMETER
UV Detect to
RST
Asserted
WDI Input Threshold
WDI Input Pull-Up Current
WDI Input Pulse Width
W/T
Threshold Voltage
W/T
Input Pull-Down Current
WDE
Threshold Voltage
WDO
Pull-Up Current (Note 6)
RST
Pull-Up Current (Note 6)
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Absolute maximum voltage at V
IN
and EN/UVLO pins is 60V for
nonrepetitive 1 second transients, and 36V for continuous operation.
Note 3:
The LT3689E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3689I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3689H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
l
l
l
The
l
denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 12V, V
OUT
= 5V, unless otherwise noted. (Note 3)
CONDITIONS
Step V
FB
from 0.9V to 0.5V
l
l
MIN
10
0.4
300
0.4
0.4
–0.6
–0.6
TYP
30
0.95
–2
0.8
2.6
0.8
–0.85
–0.85
MAX
65
1.15
UNITS
µs
V
µA
ns
1
1
V
µA
V
µA
µA
Note 4:
Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 5:
This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 6:
The output of
RST
and
WDO
has a weak pull-up to V
OUT
of
typically 1µA. However, external pull-up resistors may be used when faster
rise times are required or for V
OH
higher than V
OUT
.
Note 7:
Polarity specification for all currents into pins is positive. All
voltages are referenced to GND unless otherwise specified.
FPGA/CPLD
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