N-Channel Enhancement
Mode MOS Transistor
HCT7000M, HCT70000MTX, HCT7000MTXV
Features:
200 mA I
D
Ultra small surface mount package
R
DS(ON)
< 5Ω
Pin-out compatible with most SOT23 MOSFETS
Description:
The HCT7000M is a high performance enhancement mode N‐channel MOS transistor chip packaged in the ultra small 3 pin
ceramic LCC package. Electrical characteris cs are similar to those of the JEDEC 2N7000. The pin‐out and footprint matches
that of most enhancement mode MOS transistors built in SOT23 plas c packages.
TX and TXV devices are processed to OPTEK’s military screening program pa erned a er MIL‐PRF‐19500.
TX products receive a V
GS
HTRB at 24 V for 48 hrs. at 150° C and a V
DS
HTRB at 48 V for 260 hrs.at 150° C.
Applications:
Switching applications:
small servo motor
control, power MOSFET
gate drives
Relay Drivers
High Speed Line
Drivers
Power Supplies
Part
Number
Sensor Type
V
DSS
Min
V
GS(TH)
Min/
Max
I
D(ON)
(mA)
G
fs
(ms)
t
(ON)
/ t
(OFF)
(ns)
Min
Min
Max
Package
HCT7000M
HCT7000MTX
HCT7000MTXV
N‐Channel
Enhanced
MOSFET
60
0.8 / 3.0
75
100
10 / 10
3‐pin Ceramic
General Note
TT Electronics reserves the right to make changes in product specification without
notice or liability. All information is subject to TT Electronics’ own data and is
considered accurate at time of going to print.
© TT electronics plc
OPTEK Technology, Inc.
1645 Wallace Drive, Carrollton, TX 75006|Ph: +1 972 323 2200
www.optekinc.com | www.ttelectronics.com
Issue A
11/2016 Page 1
N-Channel Enhancement Mode
MOS Transistor
HCT7000M, HCT70000MTX, HCT7000MTXV
Absolute Maximum Ra ngs
Drain Source Voltage
Gate‐Source Voltage
Drain Current
Power Dissipa on (T
A
= 25° C)
Power Dissipa on (T
S(1)
= 25° C)
Opera ng and Storage Temperature
Thermal Resistance R
ØJC
Thermal Resistance R
ØJA
60V
±40 V
200 mA
300 mW
600 mW
(2)
‐55° C to 150° C
100° C/W
583° C/W
Electrical Characteris cs
(T
A
= 25° C unless otherwise noted)
SYMBOL
V
DSS
V
GS(TH)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
V
DS(ON)
G
fs
C
iss
C
oss
C
rss
t
(on)
t
(off)
PARAMETER
Drain Source Voltage
Gate Threshold Voltage
MIN
60
.8
75
100
MAX
3.0
±10
1
5
2.5
60
25
5
10
10
UNITS
V
V
nA
µA
mA
Ω
V
mS
pF
pF
pF
ns
ns
V
DD
= 15 V, I
D
= 0.5 A, V
gen
= 10 V, R
g
= 25Ω
V
DS
= 25 V, V
GS
= 0 V, f = 1MHz
TEST CONDITIONS
V
GS
= 0 V, I
D
= 10 µa
V
DS
= V
GS
, I
D
= 1 mA
V
DS
= 0 V, V
GS
= ±15 V
V
GS
= 0 V, V
DS
= 48 V
V
DS
= 10 V, V
GS
= 4.5 V
V
GS
= 10 V, I
D
= 0.5 A
V
GS
= 10 V, I
D
= 0.5 A
V
DS
= 10 V, I
D
= 0.2 A
Gate Leakage
Zero Gate Voltage Drain Current
On‐Site Drain Current
Drain Source on-Resistance
Drain Source on‐Voltage
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn‐on Time
Turn‐off Time
Note:
1)
T
S
= Substrate temperature that the chip carrier is mounted on.
2)
This ra ng is provided as an aid to designers. It is dependent upon moun ng material and methods and is not measurable as an outgoing test.
General Note
TT Electronics reserves the right to make changes in product specification without
notice or liability. All information is subject to TT Electronics’ own data and is
considered accurate at time of going to print.
© TT electronics plc
OPTEK Technology, Inc.
1645 Wallace Drive, Carrollton, TX 75006|Ph: +1 972 323 2200
www.optekinc.com | www.ttelectronics.com
Issue A
11/2016
Page 2
嵌入式系统
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