74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
April 1988
Revised January 2002
74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
The 74F676 contains 16 flip-flops with provision for syn-
chronous parallel or serial entry and serial output. When
the Mode (M) input is HIGH, information present on the
parallel data (P
0
–P
15
) inputs is entered on the falling edge
of the Clock Pulse (CP) input signal. When M is LOW, data
is shifted out of the most significant bit position while infor-
mation present on the Serial (SI) input shifts into the least
significant bit position. A HIGH signal on the Chip Select
(CS) input prevents both parallel and serial operations.
Features
s
16-bit parallel-to-serial conversion
s
16-bit serial-in, serial-out
s
Chip select control
s
Slim 24 lead 300 mil package
Ordering Code:
Order Number
74F676SC
74F676PC
74F676SPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2002 Fairchild Semiconductor Corporation
DS009588
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74F676
Unit Loading/Fan Out
Pin Names
P
0
–P
15
CS
CP
M
SI
SO
Description
Parallel Data Inputs
Chip Select Input (Active LOW)
Clock Pulse Input (Active LOW)
Mode Select Input
Serial Data Input
Serial Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of three modes, as
indicated in the Shift Register Operations Table.
HOLD—
a HIGH signal on the Chip Select (CS) input pre-
vents clocking, and data is stored in the sixteen registers.
Shift/Serial Load—
data present on the SI pin shifts into
the register on the falling edge of CP. Data enters the Q
0
position and shifts toward Q
15
on successive clocks, finally
appearing on the SO pin.
Parallel Load—
data present on P
0
–P
15
are entered into
the register on the falling edge of CP. The SO output repre-
sents the Q
15
register output.
To prevent false clocking, CP must be LOW during a
LOW-to-HIGH transition of CS.
Shift Register Operations Table
Control Input
Operating Mode
CS
H
L
L
M
X
L
H
CP
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Transition
X
Hold
Shift/Serial Load
Parallel Load
Block Diagram
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2
74F676
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
4.75
3.75
−0.6
−150
72
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV,
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
0V
3
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74F676
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to SO
100
4.5
5.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
110
9.0
9.0
11.0
12.5
Max
T
A
= −55°C
to 125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
45
4.5
5.0
17.0
14.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
90
4.5
5.0
12.0
13.5
Max
MHz
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(L)
t
H
(H)
Setup Time, HIGH or LOW
SI to CP
Hold Time, HIGH or LOW
SI to CP
Setup Time, HIGH or LOW
P
n
to CP
Hold Time, HIGH or LOW
P
n
to CP
Setup Time, HIGH or LOW
M to CP
Hold Time, HIGH or LOW
M to CP
Setup Time, LOW
CS to CP
Hold Time, HIGH
CS to CP
t
W
(H)
t
W
(L)
CP Pulse Width
HIGH or LOW
4.0
4.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
10.0
10.0
4.0
6.0
Max
T
A
= −55°C
to 125°C
V
CC
= +5.0V
Min
4.0
4.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
12.0
10.0
5.0
9.0
Max
T
A
, V
CC
=
____
V
CC
= +5.0V
Min
4.0
4.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
10.0
ns
10.0
4.0
6.0
ns
ns
ns
Max
Units
ns
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4
74F676
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
Package Number N24A
5
www.fairchildsemi.com
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