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74VCX162601MTDX

产品描述TXRX 18BIT UNIV BUS LV 56TSSOP
产品类别半导体    逻辑   
文件大小141KB,共10页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
标准
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74VCX162601MTDX概述

TXRX 18BIT UNIV BUS LV 56TSSOP

74VCX162601MTDX规格参数

参数名称属性值
逻辑类型通用总线收发器
电路数18 位
电流 - 输出高,低24mA,24mA;12mA,12mA
电压 - 电源1.4 V ~ 3.6 V
工作温度-40°C ~ 85°C
安装类型表面贴装
封装/外壳56-TFSOP(0.240",6.10mm 宽)
供应商器件封装56-TSSOP

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74VCX162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω
Series Resistors in the B-Port Outputs
April 1998
Revised October 2004
74VCX162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and
Outputs and 26
Series Resistors in the B-Port Outputs
General Description
The VCX162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCX162601 is designed for low voltage (1.4V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The VCX162601 is also designed with 26
series resistors
in the B-Port outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
series resistors in B-Port outputs
s
t
PD
(A to B)
3.8 ns max for 3.0V to 3.6V V
CC
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
B outputs)
±
12 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX162601MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CLKAB, CLKBA
CLKENAB, CLKENBA
A
1
–A
18
B
1
–B
18
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs
Clock Inputs
Clock Enable Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2004 Fairchild Semiconductor Corporation
DS500150
www.fairchildsemi.com

74VCX162601MTDX相似产品对比

74VCX162601MTDX 74VCX162601MTD
描述 TXRX 18BIT UNIV BUS LV 56TSSOP TXRX 18BIT UNIV BUS LV 56TSSOP
逻辑类型 通用总线收发器 通用总线收发器
电路数 18 位 18 位
电流 - 输出高,低 24mA,24mA;12mA,12mA 24mA,24mA;12mA,12mA
电压 - 电源 1.4 V ~ 3.6 V 1.4 V ~ 3.6 V
工作温度 -40°C ~ 85°C -40°C ~ 85°C
安装类型 表面贴装 表面贴装
封装/外壳 56-TFSOP(0.240",6.10mm 宽) 56-TFSOP(0.240",6.10mm 宽)
供应商器件封装 56-TSSOP 56-TSSOP

 
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