74ALVCR162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω
Series Resistors in the Outputs
September 2001
Revised October 2001
74ALVCR162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
and 26
Ω
Series Resistors in the Outputs
General Description
The 74ALVCR162601, 18-bit universal bus transceiver,
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74ALVCR162601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVCR162601 is also designed with 26
Ω
series
resistors on both the A and B Port outputs. This design
reduces line noise in applications such as memory address
drivers, clock drivers, and bus transceivers/transmitters.
Features
I
1.65–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
26
Ω
series resistors on both the A and B Port outputs.
I
t
PD
(A to B, B to A)
4.3 ns max for 3.0V to 3.6V V
CC
5.1 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
I
Power-down HIGH impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVCR162601T
Package
Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500660
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74ALVCR162601
Connection Diagram
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CLKAB, CLKBA
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A
1
–A
18
B
1
–B
18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Function Table
(Note 2)
Inputs
CLKENAB OEAB
X
X
X
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
L
L
CLKAB
X
X
X
X
X
A
n
X
L
H
X
X
L
H
X
X
Outputs
B
n
Z
L
H
B
0
(Note 3)
B
0
(Note 3)
L
H
B
0
(Note 3)
B
0
(Note 4)
↑
↑
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
HIGH Impedance
Note 2:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 3:
Output level before the indicated steady-state input conditions
were established
Note 4:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Logic Diagram
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2
74ALVCR162601
Absolute Maximum Ratings
(Note 5)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 6)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 7)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 5:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 6:
I
O
Absolute Maximum Rating must be observed.
Note 7:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −2
mA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −8
mA
I
OH
= −12
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
2 mA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
8 mA
I
OL
=
12 mA
I
OH
High Level Output Current
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3.0
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3.0
1.65
2.3
2.7
3.0
I
OL
Low Level Output Current
1.65
2.3
2.7
3.0
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V, V
I
=
V
IH
or V
IL
0V
≤
(V
I
, V
O
)
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
1.65 - 3.6
1.65 - 3.6
0
3.6
2.7 - 3.6
V
CC
- 0.2
1.2
1.9
1.7
2.4
2
2
0.2
0.45
0.4
0.55
0.55
0.6
0.8
−2
−6
−8
−12
2
6
8
12
±5.0
±10
10
40
750
µA
µA
mA
µA
µA
mA
mA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVCR162601
AC Loading and Waveforms
Table 1: Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 1. AC Test Circuit
Table 2: Variable Matrix
( Input Charactertistics: f = 1MHz; t
r
=t
f
=2ns; Z
0
= 50
Ω
)
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.7V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
FIGURE 2. Waveform for Inverting
and Non-inverting Functions
FIGURE 4. 3-STATE Output Low Enable
and Disable Times for Low Voltage Logic
FIGURE 3. 3-STATE Output High Enable
and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width
and t
rec
Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
5
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