74ALVC16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
October 2001
Revised May 2005
74ALVC16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16240 contains sixteen inverting buffers with 3-
STATE outputs to be employed as a memory and address
driver, clock driver, or bus oriented transmitter/receiver.
The device is nibble (4-bit) controlled. Each nibble has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC16240 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.0 ns max for 3.0V to 3.6V V
CC
3.5 ns max for 2.3V to 2.7V V
CC
6.0 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16240MTD
Package Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation
DS500689
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74ALVC16240
Connection Diagram
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
I
12
–I
15
L
H
X
I
8
–I
11
L
H
X
I
4
–I
7
L
H
X
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
H
L
Z
Outputs
O
4
–O
7
H
L
Z
Outputs
O
8
–O
11
H
L
Z
Outputs
O
12
–O
15
H
L
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
Functional Description
The 74ALVC16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
trolled by an Output Enable (OE
n
) input. When OE
n
is
LOW, the outputs are in the 2-state mode. When OE
n
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
Logic Diagram
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2
74ALVC16240
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 3)
DC Input Diode Current (I
IK
)
V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to 4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
V
V
V
V
Max
Units
100
P
A
4 mA
6 mA
12 mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
24 mA
100
P
A
4 mA
6 mA
12mA
24 mA
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
0
3.6
3 -3.6
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
IH
V
CC
or GND, I
O
V
CC
0.6V
r
5.0
r
10
40
750
P
A
P
A
P
A
P
A
'
I
CC
3
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74ALVC16240
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Propagation Delay
Bus to Bus
Output Enable Time
Output Disable Time
1.3
1.3
1.3
C
L
3.3V
r
0.3V
Max
3.0
4.0
4.0
50 pF
V
CC
Min
1.5
1.5
1.5
2.7V
Max
3.5
4.6
4.3
V
CC
Min
1.0
1.0
1.0
40
q
C to
85
q
C, R
L
500
:
C
L
2.5V
r
0.2V
Max
3.0
4.1
3.8
30 pF
V
CC
Min
1.5
1.5
1.5
1.8V
r
0.15V
Max
6.0
8.2
7.6
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
I
V
I
Outputs Enabled f
0V or V
CC
0V or V
CC
10 MHz, C
L
50 pF
Conditions
T
A
V
CC
3.3
3.3
3.3
2.5
25
q
C
Typical
6
7
20
20
Units
pF
pF
pF
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4
74ALVC16240
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; t
r
t
f
2 ns; Z
0
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
r
0.3V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
6V
2.7V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
6V
2.5V
r
0.2V
V
CC
/2
V
CC
/2
V
OL
0.15V
V
OH
0.15V
V
CC
*2
1.8V
r
0.15V
V
CC
/2
V
CC
/2
V
OL
0.15V
V
OH
0.15V
V
CC
*2
50
:
)
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and
Disable Times for Low Voltage Logic
5
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