电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74ACTQ244MSAX

产品描述IC BUF NON-INVERT 5.5V 20SSOP
产品类别半导体    逻辑   
文件大小102KB,共10页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
标准
下载文档 详细参数 全文预览

74ACTQ244MSAX在线购买

供应商 器件名称 价格 最低购买 库存  
74ACTQ244MSAX - - 点击查看 点击购买

74ACTQ244MSAX概述

IC BUF NON-INVERT 5.5V 20SSOP

74ACTQ244MSAX规格参数

参数名称属性值
逻辑类型缓冲器,非反向
元件数2
每元件位数4
输出类型三态
电流 - 输出高,低24mA,24mA
电压 - 电源4.5 V ~ 5.5 V
工作温度-40°C ~ 85°C(TA)
安装类型表面贴装
封装/外壳20-SSOP(0.209",5.30mm 宽)
供应商器件封装20-SSOP

文档预览

下载PDF文档
74ACQ244 • 74ACTQ244 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
July 1989
Revised November 1999
74ACQ244 • 74ACTQ244
Quiet Series Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The ACQ/ACTQ244 is an octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density. The ACQ/ACTQ uti-
lizes Fairchild Quiet Series technology to guarantee quiet
output switching and improved dynamic threshold perfor-
mance. FACT Quiet Series features GTO output control
and undershoot corrector in addition to a split ground bus
for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard AC/ACT244
Ordering Code:
Order Number
74ACQ244SC
74ACQ244SJ
74ACQ244PC
74ACTQ244SC
74ACTQ244SJ
74ACTQ244QSC
74ACTQ244MSA
74ACTQ244PC
Package Number
M20B
M20D
N20A
M20B
M20D
MQA20
MSA20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010235
www.fairchildsemi.com

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1774  1637  630  1788  2167  36  33  13  37  44 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved