74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs
February 1992
Revised June 2001
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVQ573 is functionally identical to
the LVQ373 but with inputs and outputs on opposite sides
of the package.
Features
s
Ideal for low power/low noise 3.3V applications
s
Implements patented EMI reduction circuitry
s
Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
s
Guaranteed simultaneous switching noise level
and dynamic threshold performance
s
Improved latch-up immunity
s
Guaranteed incident wave switching into 75
Ω
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ573SC
74LVQ573SJ
74LVQ573QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table
Inputs
Outputs
D
H
L
X
X
O
n
H
L
O
0
Z
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
OE
L
L
L
H
LE
H
H
L
X
H
=
HIGH Voltage
L
=
LOW Voltage
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of Latch Enable
© 2001 Fairchild Semiconductor Corporation
DS011361
www.fairchildsemi.com
74LVQ573
Functional Description
The LVQ573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D-type input changes. When LE is LOW
the latches store the information that was present on the
D-type inputs a setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LVQ573
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground
Current (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
400 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 3.0V
125 mV/ns
2.0V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
I
OLD
I
OHD
I
CC
Maximum Input Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
I
OZ
3-STATE
Leakage Current
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
3.6
±0.25
±2.5
µA
V
CC
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
4.0
0.002
T
A
= +25°C
Typ
1.5
1.5
2.99
2.0
0.8
2.9
2.58
0.1
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
36
−25
40.0
V
V
V
V
V
V
µA
mA
mA
µA
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OH
= −12
mA
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OL
=
12 mA
V
I
=
V
CC
, GND
V
OLD
=
0.8 V
Max
(Note 5)
V
OHD
=
2.0V V
Min
(Note 5)
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
3.3
3.3
3.3
3.3
0.4
−0.4
1.6
1.6
0.8
−0.8
2.0
0.8
V
V
V
V
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Units
Conditions
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for.
Note 6:
Worst case package.
Note 7:
Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8:
Max number of Data Inputs (n) switching. (n
−
1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f
=
1 MHz.
3
www.fairchildsemi.com
74LVQ573
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
t
PHL
t
PLH
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew (Note 9)
D
n
to O
n
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Min
2.5
2.5
2.5
2.5
2.5
2.5
1.0
1.0
C
L
=
50 pF
Typ
10.2
8.5
10.2
8.5
10.2
8.5
10.8
9.0
1.0
1.0
Max
14.8
10.5
16.9
12.0
18.3
13.0
20.4
14.5
1.5
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.5
2.5
2.5
2.5
2.5
2.5
1.0
1.0
Max
16.0
11.0
18.0
12.5
19.0
13.5
21.0
15.0
1.5
1.5
ns
ns
ns
ns
ns
Units
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Typ
0
0
0
0
2.4
2.0
C
L
=
50 pF
4.0
3.0
1.5
1.5
5.0
4.0
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
4.5
3.0
1.5
1.5
6.0
4.0
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
PD
(Note 10)
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
37
Units
pF
pF
V
CC
=
Open
V
CC
=
3.3V
Conditions
Note 10:
C
PD
is measured at 10 MHz.
www.fairchildsemi.com
4
74LVQ573
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
www.fairchildsemi.com
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
