74ACTQ652 Quiet Series Transceiver/Register
June 1991
Revised September 2000
74ACTQ652
Quiet Series
Transceiver/Register
General Description
The ACTQ652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The ACTQ652 utilizes Fairchild FACT Quiet Series
tech-
nology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO
output control and undershoot corrector in
addition to split ground bus for superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACTQ652SC
74ACTQ652MTC
74ACTQ652SPC
Package Number
M24B
MTC24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
7
, B
0
–B
7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010933
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74ACTQ652
Function Table
Inputs
OEAB
L
L
X
H
L
L
L
L
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
CPBA
H or L
SAB
X
X
X
X
X
X
X
X
L
H
H
SBA
X
Input
X
X
X
X
X
L
Output
X
X
H or L
H or L
H or L
X
X
H or L
H
X
Input
X
H
Output
Output
Stored B Data to A Bus
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Inputs/Outputs (Note 1)
Operating Mode
A
0
thru A
7
B
0
thru B
7
Isolation
Input
Store A and B Data
Input
Input
Not Specified
Output
Not Specified
Output
Input
Input
Input
Store B Data to A Bus
Real-Time A Data to B Bus
Output
Stored A Data to B Bus
Stored A Data to B Bus and
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
H or L
X
H or L
X
Note 1:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACTQ652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simulta-
neously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Note A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA
L
L
X
X
SAB
X
SBA
L
OEAB OEBA CPAB CPBA
H
H
X
X
SAB
L
SBA
X
Note C: Storage
Note D: Transfer Storage
Data to A or B
OEAB OEBA CPAB CPBA
X
L
L
H
X
H
X
X
SAB
X
X
X
SBA
X
X
X
FIGURE 1.
OEAB OEBA CPAB CPBA
H
L
H or L H or L
SAB
H
SBA
H
3
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74ACTQ652
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source
or Sink Current
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆
V/
∆
t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Maximum I/O
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
Maximum HIGH Level
Output Noise
Maximum LOW Level
Output Noise
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
8.0
1.5
−1.2
2.2
0.8
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
±
0.6
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
±
6.0
1.5
75
−75
80.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 3)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 3)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figures 2, 3
(Note 5)(Note 6)
Figures 2, 3
(Note 5)(Note 6)
(Note 5)(Note 7)
(Note 5)(Note 7)
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4
74ACTQ652
DC Electrical Characteristics
Note 5:
PDIP package.
(Continued)
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 6:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 7:
Max number of data inputs (n) switching. (n
−
1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
AC Electrical Characteristics
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
OSHL
t
OSLH
Parameter
Maximum Clock Frequency
Propagation Delay
Clock to Bus
Propagation Delay
Bus to Bus
Propagation Delay
SBA or SAB to A or B
Enable Time
OEBA to A (Note 8)
Disable Time
OEBA to A (Note 8)
Enable Time
OEAB to B
Disable Time
OEAB to B
Setup Time, HIGH or
LOW, Bus to Clock
Hold Time, HIGH or
LOW, Bus to Clock
Clock Pulse Width
HIGH or LOW
Output to Output Skew (Note 9)
A to B, B to A or
Clock to Output
Note 8:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any separate outputs of the same device. The spec-
ification applies to any output switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
T
A
= +25°C
C
L
=
50 pF
Min
Typ
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
Max
MHz
Units
(V)
(Note 8)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
2.0
2.5
2.0
1.0
2.0
1.0
3.0
1.5
4.0
7.0
6.5
6.5
7.0
5.0
7.0
5.0
9.5
9.0
10.0
10.5
8.0
10.5
8.0
2.0
2.0
2.5
2.0
1.0
2.0
1.0
3.0
1.5
4.0
10.0
9.5
10.5
11.0
8.5
11.0
8.5
ns
ns
ns
ns
ns
ns
ns
ns
5.0
0.5
1.0
1.0
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
54
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
5
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