74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer
February 1992
Revised June 2001
74LVQ138
Low Voltage 1-of-8 Decoder/Demultiplexer
General Description
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three LVQ138 devices or a 1-of-32 decoder using four
LVQ138 devices and one inverter.
Features
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Improved latch-up immunity
s
Guaranteed incident wave switching into 75
Ω
s
4kV minimum ESD immunity
s
Demultiplexing capability
s
Multiple input enable for each expansion
s
Active LOW mutually exclusive outputs
Ordering Code:
Order Number
74LVQ138SC
74LVQ138SJ
Package Number
M16A
M16D
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A
0
–A
2
E
1
–E
2
E
3
O
0
–O
7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011350
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74LVQ138
Functional Description
The LVQ138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A
0
, A
1
, A
2
) and,
when enabled, provides eight mutually exclusive active-
LOW outputs (O
0
–O
7
). The LVQ138 features three Enable
inputs, two active-LOW (E
1
, E
2
) and one active-HIGH (E
3
).
All outputs will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four LVQ138 devices and one inverter
(see Figure 1). The LVQ138 can be used as an 8-output
demultiplexer by using one of the active LOW Enable
inputs as the data input and the other Enable inputs as
strobes. The Enable inputs which are not used must be
permanently tied to their appropriate active-HIGH or active-
LOW state.
Logic Diagram
Truth Table
Inputs
Outputs
E
1
E
2
E
3
A
0
A
1
A
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
H
X
X
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
X
X
X
L
H
L
H
L
H
L
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
FIGURE 1. Expansion to 1-of-32 Decoding
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2
74LVQ138
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
200 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 3.0V
125 mV/ns
2.0V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
I
OLD
I
OH
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Minimum Dynamic (Note 4)
Output Current
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
V
CC
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.3
3.3
3.3
3.3
1.7
1.7
4.0
0.8
−0.8
2.0
0.8
0.002
T
A
= +25°C
Typ
1.5
1.5
2.99
2.0
0.8
2.9
2.58
0.1
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
36
−25
40.0
V
V
V
V
V
V
µA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OH
= −12
mA
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OL
=
12 mA
V
I
=
V
CC
,
GND
V
OLD
=
0.8V Max (Note 5)
V
OHD
=
2.0V Min (Note 5)
V
IN
=
V
CC
or GND
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Units
Conditions
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed.
Note 6:
Worst case package.
Note 7:
Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8:
Max number of Data Inputs (n) switching. (n
−
1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f
=
1 MHz.
3
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74LVQ138
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
OSHL,
t
OSLH
Propagation Delay
A
n
to O
n
Propagation Delay
A
n
to O
n
Propagation Delay
E
1
or E
2
to O
n
Propagation Delay
E
1
or E
2
to O
n
Propagation Delay
E
3
to O
n
Propagation Delay
E
3
to O
n
Output to Output Skew (Note 9)
Data to Output
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
C
L
=
50 pF
Typ
10.2
8.5
9.6
8.0
13.2
11.0
11.4
9.5
13.2
11.0
10.2
8.5
1.0
1.0
Max
18.3
13.0
17.6
12.5
21.0
15.0
19.0
13.5
21.8
15.5
18.3
13.0
1.5
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max
21.0
15.0
20.0
14.0
23.0
16.0
21.0
15.0
23.5
16.5
20.0
14.0
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
Units
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
C
IN
C
PD
(Note 10)
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
45
Units
pF
pF
V
CC
=
Open
V
CC
=
3.3V
Conditions
Note 10:
C
PD
is measured at 10 MHz.
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4
74LVQ138
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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