74LVT322373 • 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25Ω Series
Resistors in the Outputs
May 2002
Revised May 2002
74LVT322373 • 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25
Ω
Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs include equivalent series resistance of 25
Ω
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
74LVT322373G
(Note 1) (Note 2)
74LVTH322373G
(Note 1) (Note 2)
Package Number
BGA96A
(Preliminary)
BGA96A
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1:
Ordering Code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500742
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74LVT322373 • 74LVTH322373
Connection Diagram
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
–I
31
O
0
–O
31
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
1
A
B
C
D
E
F
G
(Top Thru View)
H
J
K
L
M
N
P
R
T
O
1
O
3
O
5
O
7
O
9
O
11
O
13
O
14
O
17
O
19
O
21
O
23
O
25
O
27
O
29
O
30
2
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
15
O
16
O
18
O
20
O
22
O
24
O
26
O
28
O
31
3
OE
1
GND
V
CC1
GND
GND
V
CC1
GND
OE
2
OE
3
GND
V
CC2
GND
GND
V
CC2
GND
OE
4
4
LE
1
GND
V
CC1
GND
GND
V
CC1
GND
LE
2
LE
3
GND
V
CC2
GND
GND
V
CC2
GND
LE
4
5
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
15
I
16
I
18
I
20
I
22
I
24
I
26
I
28
I
31
6
I
1
I
3
I
5
I
7
I
9
I
11
I
13
I
14
I
17
I
19
I
21
I
23
I
25
I
27
I
29
I
30
Truth Table
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
3
X
H
H
L
H
=
HIGH Voltage Level
Outputs
I
0
–I
7
X
L
H
X
O
0
–O
7
Z
L
H
O
0
Outputs
I
16
–I
23
X
L
H
X
O
16
–O
23
Z
L
H
O
0
X
=
Immaterial
Inputs
LE
2
X
H
H
L
OE
2
H
L
L
L
Inputs
LE
4
X
H
H
L
Z
=
HIGH Impedance
Outputs
I
8
–I
15
X
L
H
X
O
8
–O
15
Z
L
H
O
0
Outputs
I
24
–I
31
X
L
H
X
O
24
–O
31
Z
L
H
O
0
OE
3
H
L
L
L
OE
4
H
L
L
L
L
=
LOW Voltage Level
O
o
=
Previous O
o
prior to HIGH-to-LOW transition of LE
Functional Description
The LVT322373 and LVTH322373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each byte. When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input
changes. When LE
n
is LOW, the latches store information that was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
n
) input. When OE
n
is LOW, the standard outputs are in the 2-state mode. When OE
n
is HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into the latches.
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2
74LVT322373 • 74LVTH322373
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
V
CC1
is associated with Bytes 1 and 2.
V
CC2
is associated with Bytes 3 and 4.
Note:
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LVT322373 • 74LVTH322373
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
O
>
V
CC
Output at HIGH State
Output at LOW State
V
mA
mA
mA
mA
mA
−
0.5 to
+
4.6
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
50
−
50
64
128
±
64
±
128
−
65 to
+
150
°
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
−
12
12
−
40
0
85
10
°
C
ns/V
∆
t/
∆
V
Note 3:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
I(HOLD)
I
I(OD)
I
I
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
V
CC
(V)
2.7
2.7 - 3.6
2.7 - 3.6
2.7 - 3.6
3.0
2.7
3.0
3.0
3.0
3.6
3.6
3.6
0
0 - 1.5V
3.6
3.6
3.6
3.6
3.6
3.6
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
0.19
5
0.19
µA
µA
µA
µA
µA
mA
mA
mA
µA
V
CC
−
0.2
2.0
0.2
0.8
2.0
0.8
T
A
= −40°C
to
+85°C
Min
Max
−1.2
Units
V
V
V
V
V
µA
µA
Conditions
I
I
= −18
mA
V
O
≤
0.1V or
V
O
≥
V
CC
−
0.1V
I
OH
= −100 µA
I
OH
= −12
mA
I
OL
=
100
µA
I
OL
=
12 mA
V
I
=
0.8V
V
I
=
2.0V
(Note 5)
(Note 6)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V
V
I
=
GND or V
CC
V
O
=
0.5V
V
O
=
3.0V
V
CC
<
V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
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4
74LVT322373 • 74LVTH322373
DC Electrical Characteristics
Symbol
I
CCZ
+
∆I
CC
Parameter
Power Supply Current
Increase in Power Supply Current
(Note 7)
(Continued)
V
CC
(V)
T
A
= −40°C
to
+85°C
Min
Max
0.19
0.2
mA
mA
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
−
0.6V
Other Inputs at V
CC
or GND
Units
Conditions
(V
CC1
or V
CC2
)
(V
CC1
or V
CC2
)
3.6
3.6
Note 5:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 8)
T
A
=
25°C
Min
Typ
0.8
−0.8
Max
Conditions
Units
V
V
C
L
=
50 pF, R
L
=
500Ω
(Note 9)
(Note 9)
Note 8:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9:
Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
C
L
=
50pF, R
L
=
500Ω
Symbol
Parameter
V
CC
=
3.3V
±
0.3V
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Setup Time, D
n
to LE
Hold Time, D
n
to LE
LE Pulse Width
Output to Output Skew (Note 10)
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
1.0
1.0
3.0
1.0
1.0
Max
4.8
4.8
5.0
5.1
5.0
5.4
5.1
5.4
Min
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
0.8
1.1
3.0
1.0
1.0
V
CC
=
2.7V
Max
5.3
5.1
5.1
5.8
6.0
6.6
5.0
5.7
ns
ns
ns
ns
ns
ns
ns
ns
Units
Note 10:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 11)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
CC
=
Open, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Typical
4
8
Units
pF
pF
Note 11:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
5
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