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74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs
May 1995
Revised March 2001
74LCX543
Low Voltage Octal Registered Transceiver with
5V Tolerant Inputs and Outputs
General Description
The LCX543 is a non-inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Out-
put Enable inputs are provided for each register to permit
independent input and output control in either direction of
data flow.
The LCX543 is designed for low voltage (2.5V or 3.3V) V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX543 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V
−
3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
=
3.3V), 10
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA Output Drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX543WM
74LCX543MSA
74LCX543MTC
Package Number
M24B
MSA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Functional Description
The LCX543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A
0
–A
7
or
take data from B
0
–B
7
, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LCX543
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
mA
mA
mA
mA
mA
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to V
CC
+
0.5
−
50
−
50
+
50
±
50
±
100
±
100
−
65 to
+
150
°
C
Recommended Operating Conditions
(Note 4)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
=
3.0V
−
3.6V
V
CC
=
2.7V
−
3.0V
V
CC
=
2.3V
−
2.7V
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V
−
2.0V, V
CC
=
3.0V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
±
24
±
12
±
8
−
40
0
85
10
mA
°
C
ns/V
∆
t/
∆
V
Note 2:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Unused inputs or I/O's must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −12
mA
I
OH
= −18
mA
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
8mA
I
OL
=
12 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
I
I
OZ
I
OFF
Input Leakage Current
3-STATE I/O Leakage
Power-Off Leakage Current
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V
V
I
=
V
IH
or V
IL
V
I
or V
O
=
5.5V
Conditions
V
CC
(V)
2.3
−
2.7
2.7
−
3.6
2.3
−
2.7
2.7
−
3.6
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
−
3.6
0
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
10
µA
µA
µA
V
V
T
A
= −40°C
to
+85°C
Min
1.7
2.0
0.7
0.8
Max
Units
V
V
3
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74LCX543
DC Electrical Characteristics
Symbol
I
CC
∆I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
2.3
−
3.6
2.3
−
3.6
2.3
−
3.6
T
A
= −40°C
to
+85°C
Min
Max
10
±10
500
µA
µA
Conditions
V
I
=
V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V (Note 5)
V
IH
=
V
CC
−0.6V
Units
Note 5:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
V
CC
=
3.3V
±
0.3V
C
L
=
50 pF
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA to A
n
or LEAB to B
n
Output Enable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
Output Disable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
t
S
t
H
t
W
t
OSHL
t
OSLH
Setup Time, HIGH or LOW Data to LEXX
Hold Time, HIGH or LOW Data to LEXX
Pulse Width, Latch Enable, LOW
Output to Output Skew
(Note 6)
2.5
1.5
3.3
1.0
1.0
2.5
1.5
3.3
4.0
2.0
3.3
ns
ns
ns
ns
1.5
1.5
7.0
7.0
1.5
1.5
7.5
7.5
1.5
1.5
8.4
8.4
ns
1.5
1.5
1.5
1.5
1.5
1.5
Max
7.0
7.0
8.5
8.5
9.0
9.0
V
CC
=
2.7V
C
L
=
50 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
8.0
8.0
9.5
9.5
10.0
10.0
V
CC
=
2.5V
±
0.2V
C
L
=
30 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
8.4
8.4
10.5
10.5
11.0
11.0
ns
ns
ns
Units
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
FPGA/CPLD
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