74ALVC16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
October 2001
Revised October 2001
74ALVC16601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16601 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
OEAB is HIGH, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The ALVC16601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The ALVC16601 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(A to B, B to A)
3.4 ns max for 3.0V to 3.6V V
CC
4.0 ns max for 2.3V to 2.7V V
CC
7.0 ns max for 1.65V 1.95V V
CC
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16601GX
(Note 2)
74ALVC16601MTD
(Note 3)
Package Number
BGA54A
(Preliminary)
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500682
www.fairchildsemi.com
74ALVC16601
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CLKAB, CLKBA
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A
1
–A
18
B
1
–B
18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
A
2
A
4
A
6
A
8
A
10
A
12
A
14
A
16
A
17
2
A
1
A
3
A
5
A
7
A
9
A
11
A
13
A
15
A
18
3
4
5
B
1
B
3
B
5
B
7
B
9
B
11
B
13
B
15
B
18
6
B
2
B
4
B
6
B
8
B
10
B
12
B
14
B
16
B
17
OEAB CLKENAB
LEAB
V
CC
GND
GND
GND
V
CC
OEBA
CLKAB
V
CC
GND
GND
GND
V
CC
CLKBA
LEBA CLKENBA
Truth Table
(Note 4)
Inputs
CLKENAB
X
Pin Assignment for FBGA
X
X
H
H
L
L
L
L
OEAB LEAB CLKAB
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
A
n
X
L
H
X
X
L
H
X
X
Outputs
B
n
Z
L
H
B
0
(Note 5)
B
0
(Note 5)
L
H
B
0
(Note 5)
B
0
(Note 6)
↑
↑
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
(Top Thru View)
Note 4:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 5:
Output level before the indicated steady-state input conditions
were established.
Note 6:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
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74ALVC16601
Absolute Maximum Ratings
(Note 7)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 8)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 9)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 7:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 8:
I
O
Absolute Maximum Rating must be observed.
Note 9:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12mA
I
OL
=
24 mA
I
I
I
OZ
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
3.6
3 -3.6
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
40
750
µA
µA
µA
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
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