• Programmable output from 1.10V to 1.85V in 25mV steps
using an integrated 5-bit DAC
• Two interleaved synchronous phases for maximum
performance
• 100nsec transient response time
• Built-in current sharing between phases
• Remote sense
• Programmable Active Droop
(Voltage Positioning)
• Programmable switching frequency from 100KHz to
1MHz per phase
• Adaptive delay gate switching
• Integrated high-current gate drivers
• Integrated Power Good, OV, UV, Enable/Soft Start
functions
• Drives N-channel MOSFETs
• Operation optimized for 12V operation
• High efficiency mode (E*) at light load
• Overcurrent protection using MOSFET sensing
• 24 pin TSSOP package
Description
The FAN5093 is a synchronous two-phase DC-DC controller
IC which provides a highly accurate, programmable output
voltage for VRM 9.x processors. Two interleaved synchro-
nous buck regulator phases with built-in current sharing
operate 180° out of phase to provide the fast transient
response needed to satisfy high current applications while
minimizing external components.
The FAN5093 features Programmable Active Droop
for
transient response with minimum output capacitance. It has
integrated high-current gate drivers, with adaptive delay gate
switching, eliminating the need for external drive devices.
The FAN5093 uses a 5-bit D/A converter to program the
output voltage from 1.10V to 1.85V in 25mV steps with an
accuracy of 1%. The FAN5093 uses a high level of integra-
tion to deliver load currents in excess of 50A from a 12V
source with minimal external circuitry.
The FAN5093 also offers integrated functions including
Power Good, Output Enable/Soft Start, under-voltage lock-
out, over-voltage protection, and adjustable current limiting
with independent current sense on each phase. It is available
in a 24 pin TSSOP package.
Applications
•
•
•
•
Power supply for Pentium
IV
Power supply for Athlon
VRM for Pentium IV processor
Programmable step-down power supply
Block Diagram
BYPASS
6
23
R
T
+12V
18
5V Reg
UVL O
BOOT A
13
+12V
OSC
14
+
-
Digital
Control
15
+12V
17
16
BOOT B
VO
+12V
-
+
GNDA
Current
Limit
-
+
-
+
-
+
12
11
Digital
Control
10
+12V
8
9
5-Bit
DAC
1 2 3 4 5
VID0 VID2 VID4
VID1 VID3
24
Power
Good
19
PWRGD
21
7
22
ENABLE/SS
20
ILIM
DROOP/E* AGND
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.1.0 3/27/03
FAN5093
PRODUCT SPECIFICATION
Pin Assignments
VID0
VID1
VID2
VID3
VID4
BYPASS
AGND
LDRVB
PGNDB
SWB
HDRVB
BOOTB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VFB
RT
ENABLE/SS
DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA
FAN5093
Pin Definitions
Pin Number
1-5
Pin Name
VID0-4
Pin Function Description
Voltage Identification Code Inputs.
Open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 1. Internally Pulled-
Up.
5V Rail.
Bypass this pin with a 0.1
µ
F ceramic capacitor to AGND.
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
Low Side FET Driver for B.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5
"
.
Power Ground B.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
High side driver source and low side driver drain switching node B.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
High Side FET Driver B.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5
"
.
Bootstrap B.
Input supply for high-side MOSFET.
Bootstrap A.
Input supply for high-side MOSFET.
High Side FET Driver A.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5
"
.
High side driver source and low side driver drain switching node A.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
Power Ground A.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
Low Side FET Driver for A.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5
"
.
VCC.
Internal IC supply. Connect to system 12V supply, and decouple with a 10
Ω
resistor and 1
µ
F ceramic capacitor.
Power Good Flag.
An open collector output that will be logic LOW if the output
voltage is less than 350mV less than the nominal output voltage setpoint. Power
Good is prevented from going low until the output voltage is out of spec for
500µsec.
6
7
8
BYPASS
AGND
LDRVB
9
10
PGNDB
SWB
11
12
13
14
15
HDRVB
BOOTB
BOOTA
HDRVA
SWA
16
17
PGNDA
LDRVA
18
19
VCC
PWRGD
2
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
FAN5093
Pin Number
20
21
Pin Name
ILIM
DROOP/E*
Pin Function Description
Current Limit.
A resistor from this pin to ground sets the over current trip level.
Droop Control/Energy Star Mode Control.
A resistor from this pin to ground
sets the amount of droop by controlling the gain of the current sense amplifier.
When this pin is pulled high to BYPASS, the phase A drivers are turned off for
Energy-star operation.
Output Enable/Softstart.
A logic LOW on this pin will disable the output. An
10µA internal current source allows for open collector control. This pin also
doubles as soft start.
Frequency Set.
A resistor from this pin to ground sets the switching frequency.
Voltage Feedback.
Connect to the desired regulation point at the output of the
converter.
22
ENABLE/SS
23
24
RT
VFB
Absolute Maximum Ratings
(Absolute Maximum Ratings are the values beyond which the device
may be damaged or have it’s useful life impaired. Functional operation under these conditions is not implied.)
Parameter
Supply Voltage VCC
Supply Voltages BOOT to PGND
BOOT to SW
Voltage Identification Code Inputs, VID0-VID4
VFB, ENABLE/SS, PWRGD, DROOP/E*
SWA, SWB to AGND (<1µs)
PGNDA, PGNDB to AGND
Gate Drive Current, peak pulse
Junction Temperature, T
J
Storage Temperature
-55
-65
-3
-0.5
Min.
Max.
15
24
24
6
6
15
0.5
3
150
150
Unit
V
V
V
V
V
V
V
A
°
C
°
C
Thermal Ratings
Parameter
Lead Soldering Temperature, 10 seconds
Power Dissipation, P
D
Thermal Resistance Junction-to-Case,
Θ
JC
Thremal Resistance Junction-to-Ambient,
Θ
JA
16
84
Min.
Typ.
Max.
300
650
Unit
°
C
mW
°
C/W
°
C/W
Recommended Operating Conditions (See Figure 2)
Parameter
Output Driver Supply, BOOTA, B
Ambient Operating Temperature
Supply Voltage V
CC
Conditions
Min.
16
0
10.8
Max.
22
70
13.2
Units
V
°
C
V
REV. 1.1.0 3/27/03
3
FAN5093
PRODUCT SPECIFICATION
Electrical Specifications
(V
CC
= 12V, VID = [01111] = 1.475V, and T
A
= +25°C using circuit in Figure 2, unless otherwise noted.)
The
•
denotes specifications which apply over the full operating temperature range.
Parameter
Input Supply
UVLO Hysteresis
12V UVLO
12V Supply Current
Internal Voltage Regulator
BYPASS Voltage
BYPASS Capacitor
VREF and DAC
Output Voltage
Initial Voltage Setpoint
1
Output Temperature Drift
Line Regulation
Droop
2
Programmable Droop Range
Response Time
Current Mismatch
VID Inputs
Input LOW current, VID pins
VID V
IH
VID V
IL
Oscillator
Oscillator Frequency
Oscillator Range
Maximum Duty Cycle
Minimum LDRV on-time
Gate Drive
Gate Drive On-Resistance
Output Driver Rise & Fall Time
Enable/Soft Start
Soft Start Current
Enable Threshold
Power Good
PWRGD Threshold
PWRGD Output Voltage
PWRGD Delay
OVP and OTP
Output Overvoltage Detect
Over Temperature Shutdown
Over Temperature Hysteresis
Conditions
Min.
Typ.
0.5
9.5
20
5
Max.
Units
V
V
mA
V
nF
V
V
mV
µV
mV
m
Ω
nsec
%
Rising Edge
PWM Output Open
•
8.5
10.3
4.75
100
See Table 1
I
LOAD
= 0A, VID = [01111]
T
A
= 0 to 70°C
V
CC
= 11.4V to 12.6V
I
LOAD
= 69A, R
DROOP
= 13.3k
Ω
∆
V
out
= 10mV
R
DS,on
(A) = R
DS,on
(B),
I
LOAD
= 69A, Droop = 1m
Ω
V
VID
= 0.4V
-60
2.0
•
1.100
1.460
5.25
•
0
1.475
5
130
56
100
1.850
1.490
1.25
5
0.8
RT = 54.9k
Ω
RT = 137.5k
Ω
to 13.75 k
Ω
RT = 137.5k
Ω
RT = 13.75k
Ω
Sink & Source
See Figure 1, C
L
= 3000pF
•
440
200
500
90
330
1.0
20
10
ON
OFF
Logic LOW, V
VID
– V
PWRGD
I
sink
= 4mA
High
→
Low
•
1.0
0.4
85
88
500
•
2.1
130
2.2
140
40
2.3
150
92
0.4
560
2000
µA
V
V
kHz
kHz
%
nsec
Ω
nsec
µA
V
%V
OUT
V
µsec
V
°C
°C
Notes:
1. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5m
Ω
trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
2. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with VRM 9.x
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
