74VCX16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
March 1998
Revised October 2004
74VCX16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74VCX16841 is designed for low voltage (1.4V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(D
n
to O
n
)
3.0 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
±
24 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX16841MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
LE
n
D
0
–D
19
O
0
–O
19
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2004 Fairchild Semiconductor Corporation
DS500132
www.fairchildsemi.com
74VCX16841
Connection Diagram
Truth Tables
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
OE
2
H
L
L
L
D
10
–D
19
X
L
H
X
D
0
–D
9
X
L
H
X
Outputs
O
0
–O
9
Z
L
H
O
0
Outputs
O
10
–O
19
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
O
0
=
Previous O
0
before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCX16841 contains twenty D-type latches with
3-STATE outputs. The device is byte controlled with each
byte functioning identically, but independent of the other.
Control pins can be shorted together to obtain full 20-bit
operation. The following description applies to each byte.
When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the latches. In this condition the latches are trans-
parent, i.e., a latch output will change states each time its
D-type input changes. When LE
n
is LOW, the latches store
information that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition on LE
n
. The
3-STATE outputs are controlled by the Output Enable
(OE
n
) input. When OE
n
is LOW the standard outputs are in
the 2-state mode. When OE
n
is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74VCX16841
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 3)
DC Input Diode Current (I
IK
) V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
CC
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
+
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output in 3-STATE
Output Current in I
OH
/I
OL
V
CC
=
3.0V to 3.6V
V
CC
=
2.3V to 2.7V
V
CC
=
1.65V to 2.3V
V
CC
=
1.4V to 1.6V
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
1.4V to 3.6V
−
0.3V to
+
3.6V
0V to V
CC
0.0V to 3.6V
±
24 mA
±
18 mA
±
6 mA
±
2 mA
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
V
IL
LOW Level Input Voltage
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −12
mA
I
OH
= −18
mA
I
OH
= −24
mA
I
OH
= −100 µA
I
OH
= −6
mA
I
OH
= −12
mA
I
OH
= −18
mA
I
OH
= −100 µA
I
OH
= −6
mA
I
OH
= −100 µA
I
OH
= −2
mA
2.7 - 3.6
2.7
3.0
3.0
2.3 - 2.7
2.3
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
V
CC
- 0.2
2.2
2.4
2.2
V
CC
- 0.2
2.0
1.8
1.7
V
CC
- 0.2
1.25
V
CC
- 0.2
1.05
V
Min
2.0
1.6
0.65 x V
CC
0.65 x V
CC
0.8
0.7
0.35 x V
CC
0.35 x V
CC
V
V
Max
Units
3
www.fairchildsemi.com
74VCX16841
DC Electrical Characteristics
Symbol
V
OL
Parameter
LOW Level Output Voltage
(Continued)
V
CC
(V)
2.7 - 3.6
2.7
3.0
3.0
2.3 - 2.7
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.4 - 3.6
1.4 - 3.6
0
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
Conditions
I
OL
=
100
µA
I
OL
=
12 mA
I
OL
=
18 mA
I
OL
=
24 mA
I
OL
=
100
µA
I
OL
=
12 mA
I
OL
=
18 mA
I
OL
=
100
µA
I
OL
=
6 mA
I
OL
=
100
µA
I
OL
=
2 mA
Min
Max
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
±5.0
±10.0
10.0
20.0
±20.0
750
Units
V
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
IH
or V
IL
0
≤
(V
I
, V
O
)
≤
3.6V
V
I
=
V
CC
or GND
V
CC
≤
(V
I
, V
O
)
≤
3.6V (Note 5)
V
IH
=
V
CC
−0.6V
µA
µA
µA
µA
µA
µA
Note 5:
Outputs disabled or 3-STATE only.
www.fairchildsemi.com
4
74VCX16841
AC Electrical Characteristics
(Note 6)
Symbol
t
PHL
t
PLH
Parameter
Propagation Delay
D
n
to O
n
C
L
=
15 pF, R
L
=
2kΩ
t
PHL
t
PLH
Propagation Delay
LE to O
n
C
L
=
15 pF, R
L
=
500Ω
t
PZL
t
PZH
C
L
=
15 pF, R
L
=
2kΩ
t
PLZ
t
PHZ
C
L
=
15 pF, R
L
=
2kΩ
t
S
Setup Time
C
L
=
30 pF, R
L
=
500Ω
Output Disable Time
C
L
=
30 pF, R
L
=
500Ω
Output Enable Time
C
L
=
30 pF, R
L
=
500Ω
C
L
=
30 pF, R
L
=
500Ω
Conditions
C
L
=
30 pF, R
L
=
500Ω
V
CC
(V)
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
C
L
=
15 pF, R
L
=
500Ω
t
H
Hold Time
C
L
=
30 pF, R
L
=
500Ω
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
C
L
=
15 pF, R
L
=
500Ω
t
W
Pulse Width
C
L
=
30 pF, R
L
=
500Ω
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
C
L
=
15 pF, R
L
=
500Ω
t
OSHL
t
OSLH
Output to Output Skew
(Note 7)
C
L
=
15 pF, R
L
=
2kΩ
Note 6:
For C
L
=
50
P
F, add approximately 300 ps to the AC maximum specification.
Note 7:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
T
A
= −40°C
to
+85°C
Min
0.8
1.0
1.5
1.0
0.8
1.0
1.5
1.0
0.8
1.0
1.5
1.0
0.8
1.0
1.5
1.0
1.5
1.5
2.5
3.0
1.0
1.0
1.0
2.0
1.5
1.5
4.0
4.0
0.5
0.5
0.75
1.5
Max
3.0
3.4
6.8
13.6
3.5
4.4
8.8
17.6
3.8
4.9
9.8
19.6
3.7
4.2
7.6
15.2
Units
Figure
Number
Figures
1, 2
Figures
7, 8
Figures
1, 2
Figures
7, 8
Figures
1, 3, 4
Figures
7, 9, 10
Figures
1, 3, 4
Figures
7, 9, 10
ns
ns
ns
ns
ns
Figure 6
ns
Figure 6
ns
Figure 5
1.5
±
0.1
3.3
±
0.3
2.5
±
0.2
1.8
±
0.15
1.5
±
0.1
C
L
=
30 pF, R
L
=
500Ω
ns
5
www.fairchildsemi.com
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
