74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs
January 1999
Revised June 2005
74LVT16245 • 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16245),
also available without bushold feature (74LVT16245).
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 16245
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device
!
1000V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74LVT16245GX
(Note 1)
74LVT16245MEA
(Note 2)
74LVT16245MTD
(Note 2)
74LVTH16245GX
(Note 1)
74LVTH16245MEA
(Note 2)
74LVTH16245MTD
(Note 2)
Package
Number
BGA54A
(Preliminary)
MS48A
MTD48
BGA54A
(Preliminary)
MS48A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
BGA package available in Tape and Reel only.
Note 2:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500152
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74LVT16245 • 74LVTH16245
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names
OE
n
T/R
n
A
0
–A
15
B
0
–B
15
NC
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
B
0
B
2
B
4
B
6
B
8
B
10
B
12
B
14
B
15
2
NC
B
1
B
3
B
5
B
7
B
9
B
11
B
13
NC
3
T/R
1
NC
V
CC
GND
GND
GND
V
CC
NC
T/R
2
4
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
5
NC
A
1
A
3
A
5
A
7
A
9
A
11
A
13
NC
6
A
0
A
2
A
4
A
6
A
8
A
10
A
12
A
14
A
15
Truth Tables
Inputs
Pin Assignment for FBGA
OE
1
L
L
H
Inputs
OE
2
L
L
H
(Top Thru View)
T/R
2
L
H
X
Outputs
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH–Z State on A
8
–A
15
,B
8
–B
15
T/R
1
L
H
X
Outputs
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH–Z State on A
0
–A
7
,B
0
–B
7
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
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2
74LVT16245 • 74LVTH16245
Functional Description
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte
controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagrams
Note:
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LVT16245 • 74LVTH16245
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
GND
V
O
GND
Output at HIGH State, V
O
!
V
CC
Output at LOW State, V
O
!
V
CC
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
32
64
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 3:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4:
I
O
Absolute Maximum Ratings must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
(Note 5)
I
I(OD)
(Note 5)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZL
(Note 5)
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Bushold Input Minimum Drive
3.0
3.0
3.6
3.6
3.6
0
0–1.5
3.6
3.6
75
V
CC
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
V
V
2.0
0.8
T
A
40
q
C to
85
q
C
Max
Min
Units
V
V
V
I
I
Conditions
1.2
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
I
OL
I
OL
V
I
V
I
100
P
A
8 mA
32 mA
100
P
A
24 mA
16 mA
32 mA
64 mA
0.8V
2.0V
75
500
P
A
P
A
10
(Note 6)
(Note 7)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
0.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
P
A
P
A
P
A
P
A
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
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4
74LVT16245 • 74LVTH16245
DC Electrical Characteristics
Symbol
I
OZH
I
OZH
(Note 5)
I
OZH
I
CCH
I
CCL
I
CCZ
I
CCZ
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
Parameter
3-STATE Output Leakage Current
3-STATE Output Leakage Current
(Continued)
V
CC
(V)
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
T
A
40
q
C to
85
q
C
Max
5
5
10
0.19
5.0
0.19
0.19
0.2
Units
Conditions
V
O
V
O
3.0V
3.6V
Min
P
A
P
A
P
A
mA
mA
mA
mA
mA
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
'
I
CC
(Note 8)
Note 5:
Applies to bushold versions only (74LVTH16245).
Note 6:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 9)
T
A
25
q
C
Typ
0.8
Max
Units
V
V
Conditions
C
L
50 pF, R
L
(Note 10)
(Note 10)
500
:
Min
0.8
Note 9:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
Symbol
Parameter
C
L
V
CC
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 11)
Output Disable Time
Output Enable Time
Propagation Delay Data to Output
1.5
1.3
1.5
1.6
2.3
2.2
40
q
C to
85
q
C
50 pF, R
L
500
:
V
CC
Min
1.5
1.3
1.5
1.6
2.3
2.2
2.7V
Max
3.9
3.9
5.3
6.9
6.1
5.4
1.0
ns
ns
ns
ns
Units
3.3V
r
0.3V
Max
3.5
3.5
4.5
5.3
5.4
5.1
1.0
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
C
IN
C
I/O
(Note 12)
Parameter
Conditions
V
CC
V
CC
0V, V
I
0V or V
CC
0V or V
CC
3.0V, V
O
Typical
4
8
Units
pF
pF
Input Capacitance
Input/Output Capacitance
Note 12:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
5
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