74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25:
Series Resistors in the Outputs
June 1999
Revised June 2005
74LVT162240 • 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25: Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
The LVT162240 and LVTH162240 are designed with
equivalent 25
:
series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These inverting buffers and line drivers are designed for
low-voltage (3.3V) V
CC
applications, but with the capability
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Outputs include equivalent series resistance of 25
:
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Functionally compatible with the 74 series 162240
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT162240MEA
(Note 1)
74LVT162240MTD
(Note 1)
74LVTH162240MEA
74LVTH162240MEX
(Note 2)
74LVTH162240MTD
74LVTH162240MTX
(Note 2)
Package Number
MS48A
MTD48
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Note 2:
Use this Order Number to receive devices in Tape and Reel.
© 2005 Fairchild Semiconductor Corporation
DS012490
www.fairchildsemi.com
74LVT162240 • 74LVTH162240
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
Truth Table
Connection Diagram
OE
1
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Inputs
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
H
L
Z
Outputs
I
4
–I
7
L
H
X
O
4
–O
7
H
L
Z
Outputs
I
8
–I
11
L
H
X
O
8
–O
11
H
L
Z
Outputs
I
12
–I
15
L
H
X
O
12
–O
15
H
L
Z
Functional Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE standard outputs. The device is nib-
ble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins may be
shorted together to obtain full 16-bit operation. The
3-STATE outputs are controlled by an Output Enable (OE
n
)
input for each nibble. When OE
n
is LOW, the outputs are in
2-state mode. When OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LVT162240 • 74LVTH162240
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
GND
V
O
GND
V
O
!
V
CC
Output at HIGH State
V
O
!
V
CC
Output at LOW State
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
12
12
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 3:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
V
OL
I
I(HOLD)
(Note 6)
I
I(OD)
(Note 6)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power Up/Down
3-STATE Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
Output LOW Voltage
Bushold Input Minimum Drive
2.7
3.0
3.0
75
V
CC
0.2
2.0
0.2
0.8
2.0
0.8
T
A
Min
40
q
C to
85
q
C
Typ
(Note 5)
Max
Units
Conditions
V
IK
V
IH
V
IL
V
OH
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
1.2
V
V
V
V
V
I
I
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OL
I
OL
V
I
V
I
100
P
A
12 mA
100
P
A
12 mA
0.8V
2.0V
75
500
P
A
P
A
10
(Note 7)
(Note 8)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
10
0.19
5
0.19
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
3
www.fairchildsemi.com
74LVT162240 • 74LVTH162240
DC Electrical Characteristics
Symbol
I
CCZ
Parameter
Power Supply Current
Increase in Power Supply Current
(Note 9)
Note 5:
All typical values are at V
CC
3.3V, T
A
25
q
C.
Note 6:
Applies to bushold versions only (74LVTH162240).
(Continued)
T
A
Min
V
CC
(V)
40
q
C to
85
q
C
Typ
(Note 5)
Max
Units
Conditions
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
3.6
3.6
0.19
0.2
mA
mA
'
I
CC
Note 7:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 8:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 9:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 10)
T
A
Min
25
q
C
Typ
0.8
Max
V
V
Units
Conditions
C
L
50 pF, R
L
(Note 11)
(Note 11)
500
:
0.8
Note 10:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 11:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 13)
3.3V, T
A
25
q
C.
40
q
C to
85
q
C, C
L
3.3V
r
0.3V
Typ
(Note 12)
Max
4.0
4.0
4.8
4.9
4.9
4.5
1.0
50 pF, R
L
500
:
2.7V
Max
4.8
4.6
5.7
6.1
5.4
4.5
1.0
Units
V
CC
V
CC
Min
1.0
1.0
1.0
1.0
2.0
2.0
Propagation Delay Data to Output
Output Enable Time
Output Disable Time
1.0
1.0
1.0
1.0
2.0
2.0
ns
ns
ns
ns
Note 12:
All typical values are at V
CC
Note 13:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
Symbol
C
IN
C
OUT
(Note 14)
Parameter
Conditions
V
CC
V
CC
0V, V
I
0V or V
CC
0V or V
CC
3.0V, V
O
Typical
4
8
Units
pF
pF
Input Capacitance
Output Capacitance
Note 14:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
www.fairchildsemi.com
4
74LVT162240 • 74LVTH162240
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
www.fairchildsemi.com
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
